I'm trying to make a 1-bit computer, and I'm stuck on the registers. I think I am going to have 2 of them, and I want a way to separate their outputs. Let me explain. Let's say Register A has a 0, and register B has a 1. If I want to invert Register A(or do anything else with it), I would need to get a 0 on the bus. But I can't do that as long as the registers are connected, because the 1 from Register B would go into the bus and ruin the entire program. If I want to separate A and B, you would say,

  "Just use a tri-state buffer".

But why can't I just use an AND gate to separate the registers from eachother? It would block one register while letting information from the other register pass. So, are tri-state buffers even necessary?

  • \$\begingroup\$ If you want more than one functional unit output to share a bus, and especially when you are wiring up an external system using MSI/SSI logic parts, then tri-stating makes sense. You can add additional functional units to the bus without going nuts. You can, of course, require that there be only one "owner" of the bus and design it as a multi-input mux that can source from a variety of functional units. To expand the number of functional units, you'd need to break up a bus and insert another mux (and associated control line.) 6 of one, half dozen of another, in some sense. (Fine with FPGA.) \$\endgroup\$
    – jonk
    Nov 9 '19 at 20:46
  • \$\begingroup\$ This does add some clarity, since I only own discrete and SSI parts, but it doesn't explain why I shouldn't use an AND gate instead. \$\endgroup\$ Nov 9 '19 at 21:13
  • \$\begingroup\$ You'll learn soon enough when you start making stuff. It might be one of those things best learned through experience rather than "book-learned." I could try and list the ways, but I'm not in the mood to write an answer of my own. (By the way, there are also open-collector outputs and these can be simply "wire-OR'd." So that's another approach commonly used. In that case, an AND gate with an open collector output does achieve similar things to a two-quadrant + tri-state buffer output.) \$\endgroup\$
    – jonk
    Nov 9 '19 at 21:29
  • \$\begingroup\$ I think I see what you mean. If your comment was an answer I would call my case closed ;) \$\endgroup\$ Nov 9 '19 at 21:58
  • \$\begingroup\$ I could add it, I suppose. I'll keep it short, as I'm not in too much of a state for a long discourse. The sad thing is that almost anything I write has to have context. Which means perhaps drawings here. And that means unavoidable work. It may not happen right away -- an hour? Maybe more? Not sure. \$\endgroup\$
    – jonk
    Nov 9 '19 at 22:04

The other approach is to use a multiplexer, commonly called a "mux". This is a gate that uses a "select" input to choose which input to copy to its output.

If the select input is "S", then the expression for a mux is (A AND S) OR (B AND NOT S).

  • 1
    \$\begingroup\$ The problem with that is that if you have, say, 5 or 6 possible (but not simultaneous) drivers for a bus it could require an unusually complex/expensive mux arrangement where the tri-state buffer situation makes it easier/better -- especially if you need to add new subsections with the ability to also share the bus. \$\endgroup\$
    – jonk
    Nov 9 '19 at 20:40
  • \$\begingroup\$ This is true, but what if I wanted to do an operation requiring both values, such as ADD or NAND? \$\endgroup\$ Nov 9 '19 at 21:11
  • \$\begingroup\$ @TrevorMershon, you're the designer of your processor. If you can design it faster or cheaper using just AND gates instead of tri-state gates, then go ahead and do it. \$\endgroup\$
    – The Photon
    Nov 9 '19 at 23:47
  • \$\begingroup\$ In most FPGA design it's done with a MUX under the hood. I think this is the case for most current hard-wired logic, too. Tri-state buffers were great for bus technologies of the 1970's and 1980's, but I think they're passe now. \$\endgroup\$
    – TimWescott
    Nov 10 '19 at 0:56
  • \$\begingroup\$ yes a tristate buffer is precisely a way of efficiently distributing the logical function of a multiplexer to overcome fan-in issues. I don't think they are outdated. It's a common way the implicit multiplexer comprising the output stage of an ALU might be implemented for example. It's also crucial when multiple functional units must share and arbitrate the resource of a bus. \$\endgroup\$
    – vicatcu
    Nov 10 '19 at 2:14

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