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Design:

 module t_ff(q,qbar,t,clk,rst);
 input t,clk,rst;
 output reg q=0,qbar=1;

 always@(posedge clk,posedge rst)
 begin
 if(rst)begin
 q=0;
 qbar=1;
 end

 else begin
 case(t)
 1'b0:begin
      q<=q;
      qbar<=qbar;
      end

 1'b1:begin
      q<=~q;
      qbar<=~qbar;
      end

  endcase
  end
  end
  endmodule

  module mod_3_asynchronous_counter(a,abar,b,bbar,clk);
  input clk;
  output a,b,abar,bbar;
  wire rst;

  assign rst= a & b;

  t_ff one(a,abar,1'b1,clk,rst);
  t_ff two(b,bbar,1'b1,abar,rst);

  endmodule

Test_bench:

       module tb_mod_3_counter;
       reg clk;
       wire a,b,abar,bbar;

       mod_3_asynchronous_counter tb1(a,abar,b,bbar,clk);

       initial begin clk=0; end
       always begin #5 clk=~clk; end
       initial begin 
       $display ("\t\ttime\t clk\t\t {b,a}\t");
       $monitor("%d\t %b\t\t %b\t",$time,clk,{b,a});
       end

       initial begin #100 $finish; end
       endmodule

In the above verilog code, I have written module for T flip flop. Using those T FF in toggling mode, I have created asynchronous mod-3 up counter(0,1,2) as mentioned above. while simulating t_ff one is actually toggling with respect to posedge of clk. But t_ff two is not toggling with respect to posedge of abar signal.I have simulated this program in both cadence simvision & icarus verilog.

can anyone see the error in this?

why am I not getting correct output?

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If you simulate rst without any delay then you have a race condition. To see what I mean put a delay into your rst:

assign #1 rst = a & b;

and rerun your testbench. It might synthesize ok, im not sure.

In general, I recommend that if you don't have a specific reason to, you should not run different parts of your design with different clocks, and you shouldn't run asynchronous resets from anything that isn't a dedicated reset circuit. These are not hard rules, they are general recommendations.

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