I am designing a retro computer as a project to learn digital electronics hands-on (not FPGA programming). I currently have an accumulator machine similar to the PDP-8 where the ALU has the accumulator register as one of its input, the other input comes from the data bus, and the output is clocked directly into the accumulator register on the rising edge.

I can use a 74LS173 for the register, or even a 74LS161 counter (as I do for the instruction pointer, IP). But I looked if I can just replace the single register with a 74LS170 (or 670) "register file", having 4 registers, but I'm missing the clock input. It's asynchronous like my 74LS189 memory. I am looking at the 74LS670 Data Sheet particularly the timing diagrams, and I can't seem to figure out how you could read from one of the registers, into the ALU and clock the result into the same register.

I would put read select (RA, RB) and write select (WA, WB) both at the same address, say 00. Soon the data appears on Q1,2,3, and 4. Soon the result comes out of the ALU. But the timing diagram shows -WE line go low before the data arrives! That doesn't seem to make sense. Why did they build it that way? It's even worse, according to this timing diagram the data output would appear even before I lower the -WE line.

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This can't be true however, so what am I reading wrong? How did they use these register files without a clock? If I want asynchronous memory I could just use any SRAM chip.

UPDATE: It's been a veritable saga with me and these chips.

  1. Open collector logic puzzle solved, a non-issue, and moot with the '670 - Adapting the 74LS170 open-collector "register file" to active-high TTL input
  2. Wondering of to convert it to positive edge triggered - part 1 - Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous
  3. Building the positive edge detector - Positive edge detection triggers on negative edge too
  4. Trying to apply the edge detector and it doesn't work - How do I make a 74LS170 or 74LS670 register file reliably clock in data on the rising edge?

And after this circle (circus?) I am right where I started. Pulling my hair out why they never made an edge triggered register file and instead followed up the '170 with a '670 that is just as useless as the '170.

The only thing that's interesting is the dual port nature. So I can read a different register than I write to. This is the only thing that could make it somewhat useful, if the constraint is that you never write to the same register that you just read from in the immediately preceding clock cycle.

Or if you do, read and write from the same register, you must pull high the !G_W again right after the clock went high and before it goes low again. That means, I need to OR-gate this !LOAD control with a 90 degrees phase-shifted (delayed) clock, in addition to the CLOCK itself; so a 3-input OR gate:

!G_W = !LOAD + CLK' + CLK

Darn! That is complicated! So I still don't know what the use of those '170 and '670 ever was? And why the '172, which is edge triggered had been so abandoned that you can't even get an LS version for it (let alone HC?)

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    \$\begingroup\$ Write data are latched on the rising edge of write enable (as happens in any transparent latch with an active low enable) so the data is not arriving prior to the real write enable; it could be present long before the write enable goes low - the diagram is showing it clearly for the data setup time. \$\endgroup\$ – Peter Smith Nov 11 '19 at 16:15
  • \$\begingroup\$ It acts like a transparent latch - if you need to read data out, go through the ALU and back into the RAM it will work if the read and write addresses are different. To operate at the same address you need another transparent latch in the loop (or an edge-triggered register). At the time this was designed dual-port asynchronous RAMs were not available. \$\endgroup\$ – Kevin White Nov 11 '19 at 16:35
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    \$\begingroup\$ Basically it is "just any SRAM chip", and very high-tech for its day it was, too. When it came out in 1970 or whenever it was an "oh be still my heart" combination of speed, size, and power consumption. \$\endgroup\$ – TimWescott Nov 11 '19 at 16:35
  • \$\begingroup\$ @TimWescott - It's a bit more than "just any SRAM chip" as it is dual-ported. Even now they are not common. \$\endgroup\$ – Kevin White Nov 11 '19 at 18:30
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    \$\begingroup\$ @KevinWhite Yes, I glossed over that. My main point was that you can't expect a chip that was designed 50 years ago to be up to modern standards. It's almost like they had to lay out each transistor by hand, with colored plastic sticky-sheet or something! \$\endgroup\$ – TimWescott Nov 11 '19 at 19:02

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