I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections.

Could someone have a look at my diagram just to check?

Just as a heads up I know that it can be made with D flip-flops, but the logic gate board that I'll be using only contains J-K flip-flops, so I had to convert them.

Does anyone know a program that has a virtual Logic Gate Board or anything which is better than Logisim?

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  • \$\begingroup\$ Your software recommendation question is a bit unrelated to your other questions (and software recommendations are essentially product recommendations, so not greatly appreciated here). I think you really want to learn a hardware description language (Verilog, Chisel,…) and use the tools that they come with: you'll certainly not be building a large memory cell by clicking in logisim. \$\endgroup\$ – Marcus Müller Nov 11 '19 at 21:19
  • \$\begingroup\$ CLR could be Pwr On Rst, but if you clock to every bit, CLR becomes redundant \$\endgroup\$ – Tony Stewart EE75 Nov 11 '19 at 21:22
  • \$\begingroup\$ @TonyStewartSunnyskyguyEE75 Am I right in assuming that if I just take CLR out and like you said clock to every bit, that would make it a basic 4-bit series to parallel memory register? \$\endgroup\$ – Ryan Nov 11 '19 at 21:28
  • \$\begingroup\$ 1) Logisim has a D-type flip-flop. 2) Connect CLR to the asynchronous reset input; both flip-flop types have them. \$\endgroup\$ – the busybee Nov 11 '19 at 21:29
  • \$\begingroup\$ If you don't need CLR don't wire it. \$\endgroup\$ – the busybee Nov 11 '19 at 21:29

Your circuit is basically correct. You just didn't find the right pin at the bottom edge of the J-K-flip-flop. If you hover with the mouse cursor over a pin Logisim will in many cases show a little description.

  • The pin labeled "en" you connected your CLR line to shows Enable: When 0, clock triggers are ineffective.
  • The pin labeled "0" I'm using shows Clear: When 1, pin state to 0 asynchronously.

Nice, eh?

Since you are using J-K you can drop the inverters between the stages and connect J and K directly. enter image description here


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