I am given an assignment of making a guessing game for a Cyclone II FPGA in VHDL.
I have the following IBD diagram about the game:
The purpose of the game is to guess a secret number that the opponent has entered.
The description of the game says the following:
After entering the guess, a press on a button will evaluate the result as “Hi”, “Lo” or “–”. The secret number is entered manually by your opponent.
Design a game with an interface as shown in the IBD.
It needs the following functionality:
- With no keys pressed, the displays show the current input value.
- With “Set” button pressed, the input value is stored as the secret number.
- With “Show” button pressed, the secret number is displayed.
- With “Try” button pressed, the guess is evaluated and the result is displayed as “Hi”, “Lo” or “–”. The IBD shows the overall building blocks in the design.
My question is...
How would it be possible to use the "try" input that goes into the "Compare Logic" entity, when "try" is only a std_logic and not a std_logic_vector to make a guess about a number when it can only be 1 or 0 (on or off)?