I am given an assignment of making a guessing game for a Cyclone II FPGA in VHDL.

I have the following IBD diagram about the game:


The purpose of the game is to guess a secret number that the opponent has entered.

The description of the game says the following:

After entering the guess, a press on a button will evaluate the result as “Hi”, “Lo” or “–”. The secret number is entered manually by your opponent.

Design a game with an interface as shown in the IBD.

It needs the following functionality:

  1. With no keys pressed, the displays show the current input value.
  2. With “Set” button pressed, the input value is stored as the secret number.
  3. With “Show” button pressed, the secret number is displayed.
  4. With “Try” button pressed, the guess is evaluated and the result is displayed as “Hi”, “Lo” or “–”. The IBD shows the overall building blocks in the design.

My question is...

How would it be possible to use the "try" input that goes into the "Compare Logic" entity, when "try" is only a std_logic and not a std_logic_vector to make a guess about a number when it can only be 1 or 0 (on or off)?

  • \$\begingroup\$ Looks suspiciously like an assignment from my time at Aarhus University ^^ \$\endgroup\$ – Jakob Halskov Nov 12 '19 at 17:11
  • \$\begingroup\$ @JakobHalskov No one said you can't use StackExchange xD \$\endgroup\$ – user164324 Nov 12 '19 at 17:43
  • \$\begingroup\$ Should not be a problem long as it is used for clarifying the question itself. Yet you are encouraged to use your instructor for that first. \$\endgroup\$ – Eugene Sh. Nov 12 '19 at 18:00
  • \$\begingroup\$ @EugeneSh. Yes of course. However, we don't have any more lectures before the due date of this assignment, unfortunately. \$\endgroup\$ – user164324 Nov 12 '19 at 18:01
  • \$\begingroup\$ I think it depends quite a bit on how you use stackexchange. If someone here gave you a significant amount of code, which you then submitted as your own work, I would hope that you would face significant consequences. Now, I'm not saying that is your intent, it's a hypothetical comment. \$\endgroup\$ – Elliot Alderson Nov 12 '19 at 18:02

try is a trigger to guess with the input in input. input has a dual purpose - with set it is setting the secret number with try it is setting the "guess" number.

In other words, once you press try, it will perform the comparison of the value latched in Latch and the value given in input.

  • \$\begingroup\$ Ok it makes more sense now. As an additional question, do you think that the std_logic_vector for "seg" that goes from the two entities "bin2hex" into the biggest mux needs to be 14 bits long or just 7 bits? \$\endgroup\$ – user164324 Nov 12 '19 at 18:48
  • \$\begingroup\$ You have two units of bin2hex - for each digit. Each digit is represented by 7-seg display - each segment needs a bit. \$\endgroup\$ – Eugene Sh. Nov 12 '19 at 19:12
  • \$\begingroup\$ So the input in the mux needs to be 14 bits long? \$\endgroup\$ – user164324 Nov 12 '19 at 19:22
  • \$\begingroup\$ try is an enable that when false makes both P=Q and P>Q outputs of the the magnitude comparator 'Comparator logic' true, a condition that won't occur otherwise. The 4:1 'mux' multiplexer is 14 bits wide. The 'Lo', 'Hi' and '--' inputs are each comprised of two 7 segment values while the last input to 'mux' provides the two 7 segment values for the two hex digit values. \$\endgroup\$ – user8352 Nov 12 '19 at 19:23
  • \$\begingroup\$ Yes, looks like it. \$\endgroup\$ – Eugene Sh. Nov 12 '19 at 19:24

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