# PIC when generating a PWM signal does the used timer throw a overflow interrupt flag?

I'm trying to make a 10kHz PWM signal with a PIC18f25k50. Which is generated like the following diagram. I configured timer2 at 750kHz which means if I set PR2 register to 75 the comparator should reset every 100 microseconds.

datasheet PIC18(l)f2x/45k50 p179

Now the part that I dont understand is what this means for the interrupt flag of timer2. Because the timer resets at TMR2 = PR2 (it says clear timer) does this mean the interrupts is never thrown because it constantly resets before it overflows. Or does this clear signal also trigger the overflow interrupt flag.

The reason I don't understand is that later in the datasheet(15.3.2) they suggest to wait for timer2 overflow interrup flag. But how is this possible if the timer resets before that?

datasheet pic18(l)f2x/45k50 p180

## 2 Answers

Overflow in this case means a match to the preset register, which causes the timer to reset. It's spelled out better in the description of the timer that the PWM module is based on than in the description of the PWM operation itself.

14.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. Interrupt Priority is selected with the TMR2IP bit in the IPR1 register.

• So the answer is, "yes, if you enable it by setting TMR2IE"?? – Scott Seidman Nov 13 '19 at 21:00
• @ScottSeidman An interrupt is generated if TMR2IE is set, but the flag is set regardless. It can be watched for by polling, or a "while" in the main loop if other timing isn't upset by that. – Phil G Nov 13 '19 at 21:08

The TMR2IF will rise when a match between TMR2 and PR2 occures, not when the timer overflows from 0xFF to 0x00.