So to start this off I have used J-K flip flops instead of D flip flops due to the equipment that I'll be using (Logic Tutor LT345 Mk2). The first diagram I am confident is correct but the 2nd diagram being the Parallel to Parallel memory register I am unsure of. Instead of connecting Q to J, I had Q on its own as the output while connecting switched to each J input, looking back at the 2nd diagram I've taken out the input labeled Parallel Data in because I'm confident the bottom four switches will be parallel in and the above outputs being parallel out. I would appreciate anyone's input. Updated image below.

Flip Flops J K

  • \$\begingroup\$ Can you in-line the image? \$\endgroup\$
    – Transistor
    Nov 13, 2019 at 18:46
  • \$\begingroup\$ We discourage broad, open-ended design review questions here on EE.SE, because the answer(s) tend to become long strings of unrelated edits and/or comments. While this might help you with your immediate problems, it is of no value to the site overall. We DO allow design review questions in which you explain your choices and then focus on a few points about which you still have doubts. To get a better feel of what is or is not acceptable, search for "design review" on the meta site. \$\endgroup\$
    – Dave Tweed
    Nov 13, 2019 at 18:51
  • \$\begingroup\$ Expand a bit. Why are you using JK flip-flops? \$\endgroup\$ Nov 13, 2019 at 19:03
  • \$\begingroup\$ In the parallel to parallel register, what is the purpose of 'Parallel data in'? \$\endgroup\$ Nov 13, 2019 at 19:16
  • \$\begingroup\$ @Bruce Abbott I have only just noticed that and as it didnt look right during tests I removed it and now have the bottom 4 switches as my Parallel input. \$\endgroup\$
    – Meck
    Nov 13, 2019 at 19:37


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