So to start this off I have used J-K flip flops instead of D flip flops due to the equipment that I'll be using (Logic Tutor LT345 Mk2). The first diagram I am confident is correct but the 2nd diagram being the Parallel to Parallel memory register I am unsure of. Instead of connecting Q to J, I had Q on its own as the output while connecting switched to each J input, looking back at the 2nd diagram I've taken out the input labeled Parallel Data in because I'm confident the bottom four switches will be parallel in and the above outputs being parallel out. I would appreciate anyone's input. Updated image below.