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I have this circuit: Scheme

can someone explain how this circuit works?

I did Ppsice simulation for the circuit and the results: enter image description here

Simulations

I don't understand how this circuit works, on the simulations its clear that it takes Sine wave and the output is amplified square wave with the same frequency, But how it does it?

does this circuit better than the circuit suggested on this topic: Sine wave to square wave - Schmitt trigger ??

What is the purpose of Q8 on the Scheme?

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Using the simulation schematic:

Q1 and Q2 form a switchable constant current source.

  • With U1 off R1 pulls Q2's base high turning Q2 off. No current flows to the output.
  • With U1 on current is drawn from Q2's base turning it on and feeding current to the output.
  • As the output current increases a voltage drop occurs on R2. When this reaches about 0.7 V (at 70 mA) Q1 will start to turn on and steal the bias current from Q2 preventing the Q2 current from rising any further.

As a result the output will switch from 0 mA to 70 mA maximum (if the load resistance is less than about 150 Ω).

... its clear that it takes Sine wave and the output is amplified square wave with the same frequency.

The only bit remaining is understanding the operation of U1. From the Electrical Characteristics and Figure 1 of the 2N7002 datasheet we can see that the device will turn on with about 2.1 to 3 V applied to the gate. This will cause the drain-source resistance to drop to only a few ohms (see Figure 2). Thus U1 acts much like a relay would but controlled by the AC voltage applied.

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  • \$\begingroup\$ Thanks for the reply, so Q1 purpose (simulation schematic) is to prevent high current on Q2? \$\endgroup\$ – Michael Astahov Nov 13 '19 at 22:23
  • \$\begingroup\$ More usually to limit the current to the load. The most efficient thing for the transistor is to turn it completely off (no current so no power) or on as "hard" as possible (so low voltage across the transistor and low power dissipated in it). The current limiter may have a high power dissipation as the voltage across the transistor could be high and the current high at the same time. Welcome to EE.SE. \$\endgroup\$ – Transistor Nov 13 '19 at 22:38
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This is just a non-inverting buffered level-shifter with a 70 mA current limit (Ic=0.7V/10R)and high voltage gain. It could also be described as a 2.5V comparator for 0 to 12V output and ~2.5V, is the nominal FET input threshold to drive 2mA output (Id=12V/6k) with a wide tolerance as per datasheet.

It is intended for converting 5V logic levels to 12V drive levels for controlling power FETs with a controlled slew rate of dV/dt=Ic/Ciss.

Strictly speaking it can never produce a symmetrical "square wave" output unless the input is also 50% duty cycle. (But you may imagine the edges to be square)

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