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I’m looking at the CSD17303Q5 power mosfet which boasts a 100A max drain current. It confuses me why they have it in a VSON surface mount package because most pcbs would not be able to handle that kind of current by a long shot. The width of the drain and source pads are ~3mm and ~5mm. In order to carry the solicited 100A across a 3mm wide trace, you would need a 30oz cu pcb, which is absurdly big. What am I missing here?

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    \$\begingroup\$ Sure it can...as long as you force the case temperature to 25C which is what that specification indicates...which also will never be possible outside of a laboratory setting specifically meant to do that test. I would pay more mind to the SOA cruve. It places the DC operation at a more reasonable 20A, tops. \$\endgroup\$ – DKNguyen Nov 14 '19 at 0:14
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    \$\begingroup\$ @DKNguyen oh I see. I suppose that means the 100A max is referring to very short pulses of current? And is also dependent on Vds as well... \$\endgroup\$ – Ryan Nov 14 '19 at 0:20
  • \$\begingroup\$ There is (even) more to this than has been covered so far. That SOA graph is VERY pseeimistic - it specifies 99 C/W. The RthjC is under 2C/w and JA with remodest PCB copper is 49 C/W. Note they suggest 'optimised for Synchronous FET applications. Depending on duty cycle you may get several times as much mean current WHEN ON than at DC. | Put them in a say 3 phase BLDC motor driver - each is on 1/3 of the time on average (deep-ends on modulation scheme) and so the current through the bridge with sensible PCB based heatinking, thermal vias, maybe Alcore board ... \$\endgroup\$ – Russell McMahon Nov 14 '19 at 14:04
  • \$\begingroup\$ may be a lot more than the 10A DC level at 99 c/w suggests. . Some BLDCM ESC makers use rows of FETs per phase with external heatsink thermal-gooed against the array. Calculate eg Rdson x I^2 x duty cycle Watts. Now find what C/W you need to make that sensible. Currents well up from what you may think may be achievable. [[Note: I'm presently trying to optimise the cost of a high volume BLDCM ESC - this rings loud bells :-). || For simple designs something that allows you to get easy thermal connection to a "real" heatsink can be handy. \$\endgroup\$ – Russell McMahon Nov 14 '19 at 14:08
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In this case you want the track wider than or equal to length w/l>=1.

This also reduces inductance to <= 0.5nH/mm

e.g. pin 1 to 3 = 0.4x0.4mm to 2.6mm wide track minimum

With 2 oz finished tracks, each would add 0.00027 Ohms to the wider track to reach connector or load.

The Source on pins 1,2,3 might be expected to go to ground plane microvias.

Furthermore, you won't expect to find these high current ultra low RdsOn packages with thruhole packages due to the associated high effective series inductance and ringing that would result with longer lead lengths.

This is because the output Coss always increases with lower RdsOn and with risetimes <<1 us range results in degraded performance. It is also due to the the fact that inductance does not change with size, only geometric ratios.

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    \$\begingroup\$ Why would you want the track to be longer than it is wide? Seems counterintuitive to me \$\endgroup\$ – Ryan Nov 14 '19 at 0:55
  • \$\begingroup\$ oops .. I meant wider than long.. Murphy's Law. Didn't check \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 14 '19 at 1:02
  • \$\begingroup\$ Interesting. There’s a lot more to it than I thought. What formula did you use to calculate the track resistance? I’d like to use that to reference for future designs \$\endgroup\$ – Ryan Nov 14 '19 at 1:38
  • \$\begingroup\$ Saturn PCB design.exe has lots of calc's \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 14 '19 at 1:48
  • \$\begingroup\$ regarding track resistance: standard thickness (1.4 mils, 35 microns, at 1 ounce of copper foil per square foot) foil is 0.00498 (call it 0.00050) ohms per square, and is a strong function (0.4%/degree) of temperature. Notice that is per square, for any size square. As Tony Steward says "geometric ratios" are all that counts. And this applies to Via Resistance; the # squares of a Via Resistance is simply Depth/Perimeter. \$\endgroup\$ – analogsystemsrf Nov 14 '19 at 2:05
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There is (even) more to this than has been covered so far.

That datasheet SOA graph (fig 10) is VERY pessimistic - it specifies 99 C/W.
The FET's RthjC is under 2 C/W and RthJA with modest PCB copper is 49 C/W.
Note they suggest the FET is 'optimised for Synchronous FET applications'.
Depending on duty cycle you may get several times as much mean current WHEN ON than at DC. Put them in a say 3 phase BLDC motor driver - each is on 1/3 of the time on average (deep-ends on modulation scheme) and so the current through the bridge with sensible PCB based heatsinking (see photo below), thermal vias, maybe Alcore board. You should be able to achieve a lot more than the 10A DC level at 99 C/W suggests.

Some BLDCM ESC makers use rows of FETs per phase with external heatsink thermal-gooed against the array (see below).
Calculate eg Rdson x I^2 x duty cycle Watts. Now find what C/W you need to make that sensible. Currents well up from what you may think may be achievable.
[Note: I'm presently trying to optimise the cost of a high volume BLDCM ESC - this rings loud bells :-).] For simple designs something that allows you to get easy thermal connection to a "real" heatsink can be handy. TO220 and fellow travellers is good and TO247 variants are marvellous.

(I think this is a ) Maytech VESC implementation - 3 phase 120A BLDCM driver. Each (here) vertical metal strip covering 6 FEs is one 1.2 bridge high side or low side arm. N Channel FETS are used for high and low sides (as N Channel is usually lower Rdson per $ at a given Voltage) with charge pumped high side supplies.
3 black leads at bottom go to motor. Note the sprinklings of vias by each lead.
Current through FETS must flow from + or - input lead at top through plane copper then FET then plane output to motor leads. Three tubular items in tape at top are parallel electrolytic caps across power input leads.
Heatsink waits at left.

enter image description here

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  • \$\begingroup\$ Excellent (+1) Thermodynamic advice often overlooked by Electrical Engineers. SMD packages are harder to connect to external heatsinks when high power must be dissipated because they have smaller surface area. Nice thermal busbars. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 15 '19 at 17:51

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