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I have a SoC connects to a DSP with SPI. They are all powered by 1.8V, so I didn't even compare SoC's Voh and DSP's Vih at the first time, they should working fine. However, yesterday my colleague told me that the SoC's Voh cannot satisfy DSP's Vih, so I have a detail look:

You can see the SoC's Voh is at least 0.75*VDD, which is standard 1.8V CMOS Voh (Vcc-0.45). enter image description here

For the DSP's Vih, it is 0.8Vdd, which is higher than standard 1.8V CMOS Vih (0.65Vcc). DSP's Vih

So from the datasheet view, I cannot connect these SoC and DSP together? Or the minimum Voh is based on highest source current, I need to consider the output impedance of SoC, and input impedance of DSP or maybe also capacitance?

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    \$\begingroup\$ Not sure if note 30 might contain some information relevant to your question. As you don't mention the parts you use, I can't have a look myself. \$\endgroup\$ – Arsenal Nov 14 '19 at 10:30
  • \$\begingroup\$ thank you, note 30 only list which pin belongs to this group. \$\endgroup\$ – iouzzr Nov 14 '19 at 10:33
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    \$\begingroup\$ You would probably get away with connecting them directly. If you are a hobbyist, hoping one will work, go for it. If you are professional engineer, expecting to guarrantee to your customer that every one you build will work, then you're in trouble. You need a buffer, or different devices where the VOH and VIH overlap properly. The problem is noise margin, and intermittent data-dependent failures, very hard to debug. In the professional setting, if you build one, or ten, it's likely to work on the bench, and only start failing when it gets to customers, the worst possible scenario. \$\endgroup\$ – Neil_UK Nov 14 '19 at 11:39
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    \$\begingroup\$ For the Voh and Vol it's worth checking to see if any load is specified. Output levels are often specified for currents that a typical CMOS input won't even approach; they might be specified, for instance, for 5mA or 10mA, while the inputs you're driving will only require a few uA. \$\endgroup\$ – Cristobol Polychronopolis Nov 14 '19 at 13:54
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You have an almost equivalent problem with the low level signal interface between these two devices. The SOC VOL is stated to be guaranteed to be less than 0.25*DVDD.

On the other hand the VIL of the DSP states that its range for input low must be no more than 0.20*TVDD.

This spreadsheet chart illustrates both the high and low levels.

enter image description here

So if the 1.8V supplies to both parts are one and the same voltage rail you are going to have problems with guaranteed for both high and low signal levels. Buffering with a suitable external IC may be the solution to keep things simple.

Lastly I have to point out that the specifications of the SOC leave something to be desired considering the blatant carelessness pointed out below.

enter image description here

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  • \$\begingroup\$ Thank you, but as I point out, the SoC's Voh and Vol's value is standard 1.8V. On for example, NXP's logic gate (to use as buffer IC), the Voh and Vol's value is the same as this SoC's. \$\endgroup\$ – iouzzr Nov 14 '19 at 15:47
  • \$\begingroup\$ @iouzzr - The "standard CMOS" specs seem immaterial to the consideration of evaluating if the SOC could directly drive the DSP. There would be some applicability if you considered a "standard CMOS" part as a buffer for the interconnections but I would say you are way better to off studying the specs from specific data sheets rather than thinking about "standard CMOS". \$\endgroup\$ – Michael Karas Nov 14 '19 at 15:53
  • \$\begingroup\$ ok, "typical CMOS buffer" 74LVC1G34, datasheet says "IO = -4 mA; VCC = 1.65 V Voh(min) is 1.2V", voltage drop is 0.45V. So under the same load current, Vcc= 1.8V, the voltage drop should be lower than 0.45V. (1.8-0.45)/1.8 = 75% Vcc. So even if I use a buffer, the Voh is still the same. \$\endgroup\$ – iouzzr Nov 14 '19 at 16:07

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