In the Synchronous Data Link Control (SDLC) protocol, the frame contains a "frame-check-sequence" (a CRC). The protocol contains a number of other implementation details, such as NRZI encoding, and zero-bit insertion when the data contains too many contiguous 1's (so the data is not mistaken for the end-frame flag).
Three people seem to have three different interpretations on how to implement this FCS algorithm, based on the documentation not being explicit:
- One engineer says you must decode the NRZI encoding and discard the inserted-zero bits, and then the remaining bits will be pushed through a FCS algorithm.
- Another engineer says you must decode the NRZI encoding, but keep the zero-inserted bits when pumping data into the FCS algorithm.
- Another engineer says the FCS algorithm just inserts the raw data bits, not decoded and still containing inserted zero bits.
Could someone clarify which scenario is correct (or if none of them are, what is the correct sequence)? Or, if someone has an example waveform (raw logic levels as seen on the physical medium), that would help.