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I came across what look like a bug in CircuitLab, but I am not sure. There is a good chance that I am knowledgeable only to be dangerous.

In the context of How to make a 7 to 3 priority encoder? I built the beginning of my circuit with transistors and funky-diode-OR logic. And I wanted to see it simulated. But it returns wrong results. I traced it to a weird oddity on the input.

Here is my original with NPN transistors:

schematic

simulate this circuit – Schematic created using CircuitLab

Then I created a rendition with FETs and also one that is ready to be simulated. My transistor simulations were lost because CircuitLab is upselling hard if you want to work with it anywhere outside the editing of a post here.

schematic

simulate this circuit

I just tried to simulate this circuit, and found it doesn't work because the output at the emitter of the initial transistors is > 3 V even if their base is on GND. There's something wrong here either with something I'm doing with those transistors or with the simulator. I then replaced the classical NPN transistors and with FETs. The FETs switch much cleaner and don't require current at the base / gate but only potential. Yet, still J2 is having 4.5V at the drain, whereas the J1 and J3 have 4.999V. But this makes no sense. I think it is a bug in this CircuitLab site.

So, now what I'm going to do is simplify it massively to only the bug:

schematic

simulate this circuit

And here too I get > 3 V on H1, H2, and H3. Notice that the switches are inverted, tied to high and shunted to GND, don't get confused by that.

Now I will simplify it even more, to see one FET only.

schematic

simulate this circuit

I reduced it all to one single FET with gate shorted to ground, like the transistor here, and with that remaining FET I still had 4.5 V on H1. Now that I replaced the FET with the transistor, I finally get a negligible near 0 V on H1.

Now I will replace that transistor with a FET again:

schematic

simulate this circuit

So, with a FET p-channel it didn't work, but with an n-channel it worked. So if that is so, now I go back to the next bigger circuit and change the FETs.

schematic

simulate this circuit

So now that part is working and I go back to the original design only with the p-channel FETs.

schematic

simulate this circuit

And it is still not working. I suppose I am just doing that all way too naive. I guess what is happening here is that current is flowing out reversely through the gate. I don't understand FETs enough.

But I understand transistors better, and there too I find that it doesn't work in the same way.

schematic

simulate this circuit

And it is so strange V(T2.nE) is still > 3V! Even if I disconnect the emitter entirely it is > 2V! So while I could verify that the single transistor worked as I expect, now again it is behaving weird!

I'm trying it one more time to rip out all that might confuse the situation to see if T2 will finally behave!

schematic

simulate this circuit

OK, finally I traced the initial problem to the cause: somehow the diode logic is not working or is behaving erratic. I put that little momentary contact button SW4 in for testing. It should be closed to drive my logic. But once it's closed the V(T2.nE) is > 3 V but when I open it is's at near-zero. And also, if I close SW1 (short T1's base to ground), then V(T2.nE) is also OK.

It seems as if potential is leaking/breaking through the diode? How can that be?

I'm not asking you to fix my entire experiment, but perhaps telling me my main mistake?

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    \$\begingroup\$ good effort on schematic entry, but as I dislike circuitlab in favour of (free) Falstad, I have no membership. \$\endgroup\$ Nov 15, 2019 at 3:54
  • \$\begingroup\$ @TonyStewartSunnyskyguyEE75, I dislike CircuitLab very much too! It's just the default here and they are getting a massive publicity boost from this site, I think they should be less stingy or this site should replace them with the better option. I try Falstad in the future. Still, I think my problem here is real, not a bug. I just don't know enough what I'm doing it seems. \$\endgroup\$ Nov 15, 2019 at 4:05
  • \$\begingroup\$ here ya go .. the learning curve is worth it with hotkeys, drag N stretch and undocked scope options tinyurl.com/yeup2ugx just drag off gen to the side to use switches only \$\endgroup\$ Nov 15, 2019 at 4:17
  • \$\begingroup\$ no p/n just simple parameters like gain ,but add ESR to make it real for caps, inductors etc also falstad.com/circuit/e-filt-hipass-af.html no limitation for sampling time just number of samples per trace \$\endgroup\$ Nov 15, 2019 at 4:23

2 Answers 2

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The symbol you have for J2 is a JFET, not a MOSFET. They are depletion mode devices that would show the behavior you are seeing as they need a negative voltage on the gate to turn them off.

Also, measuring the voltage at the junction of a FET source and a diode can possibly be an issue because if both devices are turned off after being on, the voltage can be maintained at the node by capacitance. You can put a high-value resistor to ground to avoid the problem.

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  • \$\begingroup\$ Indeed, if I put 1 MOhm resistors on the emitters of T1, 2, and 3 to GND, this problem goes away. There is agian such a problem between T4 and T6, my poor man's AND gate. And there adding a resistor does not help. I guess that funcky diode-OR and 2-transistor AND isn't really working when putting it all together. \$\endgroup\$ Nov 15, 2019 at 5:08
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I will try my own answer here although it's not complete.

I made several severe rookie mistakes. I thought I understood transistors and diodes, but my intuition didn't pan out.

And that's not even to mention my confusion with JFETs vs MOSFETs.

This what I drew isn't really the way TTL (or RTL or any logic gates are constructed.) And MOSFETs and conventional transistors don't work the same way either.

In this simulator experiment I have 4 circuits:

  1. Simple investing buffer in CMOS, is super nice in that it switches perfectly between 5V and almost complete 0V, and without any actual current needing to flow in steady state, only tiny currents during switching between states. It seems more complex than transistor + resistor, on a chip, however, it is way more space efficient. Unfortunately it always inverts the signal and gates get complicated quickly.
  2. This does not simply translate to a pair of PNP - NPN transistors. When the switch is closed, and pulls the bases to GND, there is still a voltage of 4.5V at the collector of T1n. Why? It's complicated and I don't even need to know. It just doesn't work like that.
  3. Now the mystery of the funky-diode-OR gate: it just doesn't work that way. While the diodes will perhaps stop current from flowing backwards they do not stop potential from propagating backwards apparently.
  4. I don't even need a transistor to show the diode problem. Even though I have a huge resistor (or no connectivity at all, like an open switch), the anode of D4 has potential at around 4.2V just because of D7. It just doesn't work that way.

schematic

simulate this circuit – Schematic created using CircuitLab

So I should scrap my naive attempt to implement the complex logic in this way altogether it just doesn't work like that.

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