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Using a 74LVC163 synchronous 4-bit binary counter and would like to predicate the counting on an asynchronous signal. If I apply this signal directly to one of the enables (e.g. CEP), am I assured that the counter will either count or not count when clocked? Or might it get into a metastable funk if clocked when the enable is neither high nor low? (Possibly resulting in outputs changing long after a clock, for example.)

If metastability is a concern in this scenario, I can synchronize the enable signal through a couple of flip-flops before it reaches the counter. Not a HUGE deal. Just wondering if that's truly necessary for reliable operation. If it isn't, I'd love to save an IC.

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  • \$\begingroup\$ does the datasheet show required setup and hold time, on the"enable" input? \$\endgroup\$ Nov 15 '19 at 15:57
  • \$\begingroup\$ Yes, all the inputs do have setup and hold times. \$\endgroup\$
    – Aaron
    Nov 15 '19 at 16:16
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Yes, it is necessary. All control inputs to a '163 have setup and hold requirements with respect to the clock input.

And the issue is not just metastability. There are four individual FFs inside the chip, and if the setup/hold requirements are not met, they might interpret the control inputs differently (because of varying internal path delays), leading to unexpected state transitions.

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  • \$\begingroup\$ Thanks Dave. I was leaning that way, and then wondered if I was being silly. It's easy enough to drop a couple of flip-flops in there, so I'll just do it. And thanks for the additional clarity about the possible misbehavior. That certainly makes sense! Electronics hobbyist here. Still grappling with these things. \$\endgroup\$
    – Aaron
    Nov 15 '19 at 16:15

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