Using a 74LVC163 synchronous 4-bit binary counter and would like to predicate the counting on an asynchronous signal. If I apply this signal directly to one of the enables (e.g. CEP), am I assured that the counter will either count or not count when clocked? Or might it get into a metastable funk if clocked when the enable is neither high nor low? (Possibly resulting in outputs changing long after a clock, for example.)
If metastability is a concern in this scenario, I can synchronize the enable signal through a couple of flip-flops before it reaches the counter. Not a HUGE deal. Just wondering if that's truly necessary for reliable operation. If it isn't, I'd love to save an IC.