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Let's say you have a project in VHDL that looks something like this:

enter image description here

Generally it's pretty easy to map the ports together between Component 1 and Component 2. However, what if Component 1 is code from another VHDL project that you created earlier, such as a binary to seven segment decoder, which also contains components inside it that has been port mapped together as well. Then how do you Integrate Component 1 into the final project (the Top Module) and map it together with Component 2, when Component 1 already contains components that has been mapped together?

Could someone provide an example?

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  • \$\begingroup\$ you can't label something "reusable" and have it do physical pin mappings. That is not reusable, at all! \$\endgroup\$ – Marcus Müller Nov 16 '19 at 15:18
  • \$\begingroup\$ @MarcusMüller I edited that. \$\endgroup\$ – user164324 Nov 16 '19 at 15:24
  • \$\begingroup\$ You have not well defined your problem, perhaps provide code (or pseudo code) rather than a picture? I think what you want is the 'configuration' statement. This allow you to define functional 'sockets' and plug 'components' into those sockets. Effectively this allows you to construct a new top level from a disparate selecton of modules from other places. I won't put this as an answer though as I'm not really sure I understand what you are asking. \$\endgroup\$ – Jason Morgan Nov 16 '19 at 15:40
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I've never seen components "encapsulate" any external pin mappings – they are, instead, logical modules with a clear interface.

The external pin mapping is done on a project, not on the component level.

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The usual approach that I use when doing a complete chip design is to separate the functional core logic from anything having to do with the chip's physical interface.

This core logic module can be instantiated twice — once in a functional simulation testbench, and again in a top-level module that also includes any logic specific to the physical I/O such as tristate buffers and PLLs. Here's a generic block diagram:

schematic

simulate this circuit – Schematic created using CircuitLab

The physical constraints file only applies to the top-level synthesis module, "CHIP_top". All other modules are purely logical.

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Same way as shown here in the question.

If C1 contains other components, they are either interconnected via signals internal to C1 (which we can ignore) or brought out as ports on C1 (which we just connect as above).

If that doesn't answer your concerns, you'll need to refine the question.

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