Let's say you have a project in VHDL that looks something like this:
Generally it's pretty easy to map the ports together between Component 1 and Component 2. However, what if Component 1 is code from another VHDL project that you created earlier, such as a binary to seven segment decoder, which also contains components inside it that has been port mapped together as well. Then how do you Integrate Component 1 into the final project (the Top Module) and map it together with Component 2, when Component 1 already contains components that has been mapped together?
Could someone provide an example?