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While looking at the L6470 stepper driver datasheet I came across the following charge pump circuit suggestion (I will just name it Variant A). The charge pump is used to provide the "Bootstrap voltage needed for driving the high-side power DMOS of both bridges" 1.

Variant A

As a beginner, so far I only knew about the circuit below (say, Variant B). enter image description here

My questions are:

  • What are the advantages of two different charge pump circuit variants?
  • Are both interchangeable?
  • Do applications exist where one of them is the preferred choice?

To get a better understanding, I tried both variants in the simulator on falstad.com (see link for live circuit).

I used a resistor (10k) as load in both cases. Is this maybe inadequate as variant A is used to charge the power mosfet gates?

So far my conclusion is that Variant A requires a smaller voltage rating for the second capacitor, but seems to draw more current from the main source.

Thank you!

L6470 stepper driver datasheet

live circuit

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  • \$\begingroup\$ Note that a DC current does not flow through a capacitor so it doesn't affect the amount of DC current from the source where you connect the capacitor. \$\endgroup\$ – Kevin White Nov 17 '19 at 1:13
  • \$\begingroup\$ But he is referring to the AC current due to bipolar currents vs unipolar currents \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 17 '19 at 4:50
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I had not evaluated these differences before.

I changed the simulation for a 12V DC supply with gen. being the low side Nch PWM 12V pulse with 10% duty cycle at 10kHz for Circuits "A" and "B". This is a better simulation since the PWM on the low side is the same as the Vdc source.

Then I used a load of 10 Ohms 10nF for a power FET gate impedance.

Then knowing that e-caps of this size in Alum Electr. have a ESR*C =T value of <10us for low ESR and 100~200us for General Purpose. I showed a top and bottom pair of A,B ccts with low ESR and GP caps.

My conclusion was the noise, ripple, current and voltage start ramp characteristics were not significantly different between A&B. But there was a significant difference between GP and low ESR Caps making these justifiable as the voltage rise above threshold reduces the RdsOn by the square of the difference towards the minimum which is important for lower value supply voltages such as 12V with std 4V Vgs(th) FETs.

10uF e-cap SIM

enter image description here

My conclusion was that although cct A has a minor advantage of a lower Vdc across the diode pair, stocking these extra unique parts might be more hassle than it's worth, especially if they got swapped.

Then look at the suggested cap sizes perhaps for higher PWM , but I kept it at the same but reduced the ESR according to my experience with low ESR and GP ceramic caps. The rise time of Boost voltage takes more pulses and thus the high side drivers may get warmer on startup with smaller values but lower ESR ceramic caps do make a difference if Power FETs are used.

Ref P19 of datasheet for cap values (typ)

10nF+220nF Ceramic Cap SIM

Estimate or ESR C values with ramp up of boost voltage after 1ms

enter image description here

Top right is best "B" low ESR

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  • \$\begingroup\$ Thank you for looking into this. Adding the ESR is something that did not occur to me, thank you! Is a 10 Ohms resistor in series with a 10nF capacitance (or the adequate total gate charge Qg) a common way to model the gate charging? Also, would you agree with my early conclusion regarding the voltage rating and the load of the main source (is there a better way to say this)? Thank you! \$\endgroup\$ – 0laf Nov 17 '19 at 18:33
  • \$\begingroup\$ see IC datasheet p19 for common values C BOOT 220 nF C FLY 10 nF \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 17 '19 at 19:11
  • \$\begingroup\$ Lower Voltage rating will not improve performance nor save significant cost or size and 10uF is not common for this chip . but 10 ohm 10nF for Rg, Ciss may be some power NFETs as PWM rates increase in f .. read/compute specs for RLC impedance where appropriate and include in model/sim for any part. so A vs B depends on losses from Vdd and rise time. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 17 '19 at 19:13

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