I had not evaluated these differences before.
I changed the simulation for a 12V DC supply with gen. being the low side Nch PWM 12V pulse with 10% duty cycle at 10kHz for Circuits "A" and "B". This is a better simulation since the PWM on the low side is the same as the Vdc source.
Then I used a load of 10 Ohms 10nF for a power FET gate impedance.
Then knowing that e-caps of this size in Alum Electr. have a ESR*C =T value of <10us for low ESR and 100~200us for General Purpose. I showed a top and bottom pair of A,B ccts with low ESR and GP caps.
My conclusion was the noise, ripple, current and voltage start ramp characteristics were not significantly different between A&B. But there was a significant difference between GP and low ESR Caps making these justifiable as the voltage rise above threshold reduces the RdsOn by the square of the difference towards the minimum which is important for lower value supply voltages such as 12V with std 4V Vgs(th) FETs.
10uF e-cap SIM
My conclusion was that although cct A has a minor advantage of a lower Vdc across the diode pair, stocking these extra unique parts might be more hassle than it's worth, especially if they got swapped.
Then look at the suggested cap sizes perhaps for higher PWM , but I kept it at the same but reduced the ESR according to my experience with low ESR and GP ceramic caps. The rise time of Boost voltage takes more pulses and thus the high side drivers may get warmer on startup with smaller values but lower ESR ceramic caps do make a difference if Power FETs are used.
Ref P19 of datasheet for cap values (typ)
10nF+220nF Ceramic Cap SIM
Estimate or ESR C values with ramp up of boost voltage after 1ms
Top right is best "B" low ESR