My gut tells me so, but the proof eludes me. Effectively this output is the AND of all four bits. These four bits go from 0 to 1 at very distinct times, assuming the counter is running at a reasonable clock rate. From this, I assume that the TC output's transition from 0 to 1 is safe. But what about the other way? When the counter rolls over and all bits go from 1 to 0, may I assume that TC makes a glitch-free transition from 1 to 0 as well? I sense that I'm missing some elementary rule of thumb here.
No, I don't think you can assume it will be glitch free.
The problem is not that the expected low to high and high to low transitions will be glitchy, in fact those transitions are likely to be glitch-free.
The problem rather is that the output may briefly glitch high during counting. For example during the transition from 1101 to 1110 if the units flip-flop is slightly slower than the twos flip-flop then the data outputs may briefly be 1111 and thus the TC/RCO output may briefly go high.
I'm assuming that you are referring to RCO, the ripple-carry output, rather than TCO.
No, you can not assume that it is glitch-free. In fact, the Texas Instruments datasheet says
counting spikes may occur on the (RCO) ripple carry output