CD4006 Behavioral model in LTSpice

I want to simulate the behavioral model of CD4006 chip in LTspice. It is a CMOS 18-Stage Static Register. Looking at the Datasheet I see the one stage logic diagram that consist of inverting buffers and flops. But this stage has D, Q, !Q, CL and !CL i/os. CL - is for clock. D - is for DATA, Q and !Q - outputs, but what is the !CL input ? Is it CLR, that is usual attribute for FLOPs in LTspice?

1 Answer

At the top of page 6 in the datasheet is a small diagram showing how each flip-flop is constructed from transmission gates and inverters. The transmission gates need both the true and complement of the clock, and it is often easier to generate these globally for all of the flip-flops rather than internal to each flip-flop. So, !CL (or $$\\overline{CL}\$$) is just the complement of the clock signal.

• Are the Transmission Gates used in CD40xx series are the same? Like rghost.net/7nTB9Yncn this one ? – Roman Nov 19 '19 at 0:06
• And Inverting Buffers, like here rghost.net/7vmD4Dfg8 ? – Roman Nov 19 '19 at 0:08
• Sorry, I'm not visiting your random links. They are standard transmission gates, standard inverters, used to build a standard CMOS latch. – Elliot Alderson Nov 19 '19 at 2:09