This is with reference to this question and this App Note

In the App note, Page 4, it discusses about the steps for multimaster which I have mentioned it below :

" The following describes the procedures for the operation of this sample task.

  1. The I2 C bus interface multi-master transfer starts on the input of the low trigger to the IRQ0 pin of the master side.
  2. The master side transmits 128 bytes of data, which have been prepared in the on-chip ROM in advance, to the onchip RAM on the slave side.
  3. The slave device returns the 128 bytes of data received in step 2 from its on-chip RAM to the on-chip RAM on the master side.
  4. The master side compares the received data in its on-chip RAM with the data transmitted from its on-chip ROM, and confirms whether the two match.
  5. Based on the results of this comparison and the state of arbitration lost, the master side outputs levels on the PE2 to PE0 pins that indicate the result of operation.
  6. From the value of the first byte of received data on the slave side, the slave judges whether the partner in communications is master 1 or master 2, and outputs levels on pins P15 and P14 that indicate the state of operation. "

I was not able to understand point 5 and point 6.

What do they mean by "State of Arbitration Lost" and why do we need to show the result of the operation on Pins PE2-PE0? Are we not wasting pins?

Why don't we just send the I2C Signals once, the point 4 is completed and the comparison is satisfied?

  • \$\begingroup\$ Please add the text to your question, don't ask people to follow links and have to find information. The better the quality of your question, the better the quality of the answers you will attract. \$\endgroup\$
    – TonyM
    Nov 19 '19 at 12:01
  • 1
    \$\begingroup\$ edited my question \$\endgroup\$
    – Newbie
    Nov 19 '19 at 12:14
  • 1
    \$\begingroup\$ The comparison checks whether all transmission have worked correctly. If arbitration was lost, there was no complete transmission. \$\endgroup\$
    – CL.
    Nov 19 '19 at 12:25
  • 1
    \$\begingroup\$ PE0 to PE2 are debug outputs. \$\endgroup\$
    – Janka
    Nov 19 '19 at 12:55

About the question about PE2-PE0 being a waste of pins. Maybe not because the master who lost the arbitration may need to retry the transmission. To understand better the use of these pins, you should go deeper in the device datasheet (as opposed to the App Note.)

Hopefully this will help you to understand point 5 and 6

I am assuming you are familiar with the open collector/open drain configuration. As you know, communication is made over only two lines namely SDA and SCL.

Now, lets focus on the data line (SDA.) SDA can be in two states:

  1. Pulled up: No transistor is driving the line down. The voltage on the line is Vcc/Vdd (+).
  2. Driven down: One (or more) transistors are pulling the line down. The voltage on the line is Vee/Vss.

Now, let's say two masters want to take the bus exactly at the same time. They will take the bus if no start has been sent before. So they will send the data but keep monitoring the data line. At any time, there are four possibilities:

  1. None of the masters pull the line down (is not a problem as there is no conflict.)
  2. Both masters pull the line down (there is no conflict either.)
  3. Master A is driving the line down but Master B is not. Master A does not detect conflict so it keeps transmitting. Master B senses that the line is high but as Master B is not driving the line down, it detects the conflict and stops transmitting.
  4. Master B is driving the line down but Master A is not. In this case A detects the conflict and stops transmitting.
  • \$\begingroup\$ Good answer, upvoted, but recessive and active are CAN terminology and confusing to read - please fix to 'driven low' and 'pulled high'. \$\endgroup\$
    – TonyM
    Nov 19 '19 at 13:52
  • \$\begingroup\$ Hello @TonyM the terms are not exclusive for CAN bus. Actually, the correct terms are dominant and recessive (so I was in an error there.) However, I agree that the terminology you propose is clearer so I edited accordingly. \$\endgroup\$
    – Krauss
    Nov 19 '19 at 18:41

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