For a project I am working on I need to transfer, without loss of information, continous data bursts at a maximum of 48 MB/s from an FPGA to a mass storage device.

An SD card device (with appropriate SD Host controller) could give random delays up to approx. 500 ms. I don't know the USB standard in detail so I could not argue about possible delays.

In any case any kind of delay implies the use of an intermediate FIFO.

What could be the best solution to achieve this kind of transfer & storage ?

  • 2
    \$\begingroup\$ DRAM? This is usually the standard approach. 500 ms is only 24 MB anyway. You can probably get away with static RAM. Does the SD system have enough throughput. 48 MB/s is approaching HDD speeds. \$\endgroup\$
    – user110971
    Nov 19, 2019 at 13:43
  • \$\begingroup\$ What is the total amount of data to be stored without a pause in transmission? \$\endgroup\$ Nov 19, 2019 at 13:46
  • \$\begingroup\$ Elliot, the amount can range from 48 MB to approx. 30 GB. \$\endgroup\$
    – xyx
    Nov 19, 2019 at 14:24
  • 2
    \$\begingroup\$ It sounds like SD card is the correct final destination, but you'll also need some external SDRAM to use as a buffer. \$\endgroup\$
    – Dave Tweed
    Nov 19, 2019 at 14:29

2 Answers 2


This sounds like it could be a good application for an SoC like a Zynq. Stream the data into DRAM, then let Linux handle writing it out to some form of storage (SD card, USB key, etc.) No need to implement a full filesystem stack in HDL if you can avoid it.


Easy option 1:

Stream it to a PC using UDP/IP over Gigabit Ethernet. That way you only need minimum FIFO buffering. Risk: You need to bet on that Ethernet cable and the receiving PC software being lossless.

Easy option 2:

Use a FTDIchip FT600. It is a USB IC which is easy to interface from FPGA, and it has 16kByte built-in FIFO. Bandwidth is supposedly 5Gbit/s. Risk: Not sure if that FIFO can guarantee no FIFO overrun at all times. Not sure if this thing can actually maintain the continuos bandwidth you need. https://www.ftdichip.com/Products/ICs/FT600.html

Easy option 3:

A very large bank of QSPI flash memories. Stagger writes between the memories to avoid the need for a large FIFO. Disadvantage: It would require a LOT of QSPI memories.

Easy option 4:

Stream the data to a dedicated data capture card. Disadvantage: Expensive.

More difficult options:

  • SD card with large DRAM FIFO.

  • Or use several SD cards, and stagger writes between the cards to avoid the need for a large FIFO.

  • Or build your board as a PCI Express card, and stream to PC main memory.

  • Or use a Xilinx zynq, and let software handle the large FIFO, and streaming to SD card, Ethernet or USB. Risk: It would not be easy to achieve that bandwidth in Linux software on a zynq. If you make your DRAM large enough to hold all your data, then the software bandwidth becomes less important. But that is a lot of DRAM. Not sure if the zynq can handle that.


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