Is it possible to create a 24x16 multiplier using DSP48E slice from a 25x18 dedicated multiplier in Virtex-7? Please post a sample code... Are any advanced multipliers of these available?

  • \$\begingroup\$ Your question body does not match your question title. Your question body also doesn't make sense. \$\endgroup\$ – DKNguyen Nov 19 '19 at 18:22
  • \$\begingroup\$ Edit your question properly in consistent with the title ... \$\endgroup\$ – Mitu Raj Nov 19 '19 at 18:48
  • \$\begingroup\$ The vhdl tag is for VHDL (Very high scale integrated circuit Hardware Description Language) not Verilog. \$\endgroup\$ – user8352 Nov 19 '19 at 22:00
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    \$\begingroup\$ Vasudeva - Why did you change the text to ask about creating a 24x16 multiplier instead of a 48x48 multiplier? If it's a new problem you are having, it is better to ask a new question so that the answer already below matches the original question. Thanks! \$\endgroup\$ – Justin Nov 20 '19 at 17:56
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    \$\begingroup\$ You are still asking about dogs with title cats. \$\endgroup\$ – Mitu Raj Nov 21 '19 at 17:17

DSP48E1 slice in 7-series Xilinx FPGAs contains a 25x18 multiplier. You can make use of those DSP slices in your FPGA to implement bigger multipliers.

Following simple behavioral code inferred me a 48x48 multiplier using DSP slices on Virtex-7, when synthesised in Vivado. Vivado synthesiser is smart enough to map the logic automatically to DSP slices, which you can see in the synthesis report.

library IEEE;

entity Multiplier_VHDL is
      x, y       : in std_logic_vector(47 downto 0);
      clk, rst   : in std_logic;
      result     : out std_logic_vector(95 downto 0)
end entity Multiplier_VHDL;

architecture Behavioral of Multiplier_VHDL is
      if rst = '0' then
         result <= (others => '0');
      elsif rising_edge(clk) then
         result <= std_logic_vector(unsigned(x) * unsigned(y));
      end if;
   end process;
end architecture Behavioral; 

enter image description here

P.S I am a VHDL guy. You can try the same in Verilog.

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    \$\begingroup\$ In Verilog we do the same. Just multiply two 48 bit vectors (signed or unsigned) and Xilinx will cascade the multipliers for you. \$\endgroup\$ – Oldfart Nov 19 '19 at 18:40
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    \$\begingroup\$ yea, but without the headache of type conversions ;) \$\endgroup\$ – Mitu Raj Nov 19 '19 at 18:45
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    \$\begingroup\$ @MituRaj if X, Y, and result were defined as unsigned to begin with on the ports, there would be no type conversions. The type conversions were just a result of how the entity was defined in this case, not anything inherent to VHDL (other than that VHDL is strongly typed). \$\endgroup\$ – user4574 Nov 19 '19 at 20:08
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    \$\begingroup\$ That's right. But std logic vector is still the standard interface used by most IPs. So I personally prefer that on top level ports for ease of portability. \$\endgroup\$ – Mitu Raj Nov 19 '19 at 20:11

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