How to implement a 48x48 multiplier using DSP48E slices in Verilog HDL?

Question

Is it possible to create a 24x16 multiplier using DSP48E slice from a 25x18 dedicated multiplier in Virtex-7? Please post a sample code... Are any advanced multipliers of these available?

Answer 1

DSP48E1 slice in 7-series Xilinx FPGAs contains a 25x18 multiplier. You can make use of those DSP slices in your FPGA to implement bigger multipliers.

Following simple behavioral code inferred me a 48x48 multiplier using DSP slices on Virtex-7, when synthesised in Vivado. Vivado synthesiser is smart enough to map the logic automatically to DSP slices, which you can see in the synthesis report.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Multiplier_VHDL is
   port
   (
      x, y       : in std_logic_vector(47 downto 0);
      clk, rst   : in std_logic;
      result     : out std_logic_vector(95 downto 0)
   );
end entity Multiplier_VHDL;

architecture Behavioral of Multiplier_VHDL is
begin
   process(clk)
   begin
      if rst = '0' then
         result <= (others => '0');
      elsif rising_edge(clk) then
         result <= std_logic_vector(unsigned(x) * unsigned(y));
      end if;
   end process;
end architecture Behavioral; 

P.S I am a VHDL guy. You can try the same in Verilog.