# How to implement a 48x48 multiplier using DSP48E slices in Verilog HDL?

Is it possible to create a 24x16 multiplier using DSP48E slice from a 25x18 dedicated multiplier in Virtex-7? Please post a sample code... Are any advanced multipliers of these available?

• Your question body does not match your question title. Your question body also doesn't make sense. – DKNguyen Nov 19 '19 at 18:22
• Edit your question properly in consistent with the title ... – Mitu Raj Nov 19 '19 at 18:48
• The vhdl tag is for VHDL (Very high scale integrated circuit Hardware Description Language) not Verilog. – user8352 Nov 19 '19 at 22:00
• Vasudeva - Why did you change the text to ask about creating a 24x16 multiplier instead of a 48x48 multiplier? If it's a new problem you are having, it is better to ask a new question so that the answer already below matches the original question. Thanks! – Justin Nov 20 '19 at 17:56
• You are still asking about dogs with title cats. – Mitu Raj Nov 21 '19 at 17:17

DSP48E1 slice in 7-series Xilinx FPGAs contains a 25x18 multiplier. You can make use of those DSP slices in your FPGA to implement bigger multipliers.

Following simple behavioral code inferred me a 48x48 multiplier using DSP slices on Virtex-7, when synthesised in Vivado. Vivado synthesiser is smart enough to map the logic automatically to DSP slices, which you can see in the synthesis report.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Multiplier_VHDL is
port
(
x, y       : in std_logic_vector(47 downto 0);
clk, rst   : in std_logic;
result     : out std_logic_vector(95 downto 0)
);
end entity Multiplier_VHDL;

architecture Behavioral of Multiplier_VHDL is
begin
process(clk)
begin
if rst = '0' then
result <= (others => '0');
elsif rising_edge(clk) then
result <= std_logic_vector(unsigned(x) * unsigned(y));
end if;
end process;
end architecture Behavioral;


P.S I am a VHDL guy. You can try the same in Verilog.

• In Verilog we do the same. Just multiply two 48 bit vectors (signed or unsigned) and Xilinx will cascade the multipliers for you. – Oldfart Nov 19 '19 at 18:40
• yea, but without the headache of type conversions ;) – Mitu Raj Nov 19 '19 at 18:45
• @MituRaj if X, Y, and result were defined as unsigned to begin with on the ports, there would be no type conversions. The type conversions were just a result of how the entity was defined in this case, not anything inherent to VHDL (other than that VHDL is strongly typed). – user4574 Nov 19 '19 at 20:08
• That's right. But std logic vector is still the standard interface used by most IPs. So I personally prefer that on top level ports for ease of portability. – Mitu Raj Nov 19 '19 at 20:11