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I am interested in implementing an ASCII-based communication protocol in Verilog for an FPGA. The communication protocol is FIX, and would require various string manipulations.

What tools/libraries should I use for synthesisable string manipulation?

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    \$\begingroup\$ Hi Randomblue! Did you mean to write two different questions, both similar? Do you expect different answers? \$\endgroup\$
    – clabacchio
    Oct 30, 2012 at 10:26
  • \$\begingroup\$ Hi back. I was intending one question to be specific to SystemVerilog, which is a language I do not know, and the other question to be specific to Verilog, which is a language I do know. I'd be happy to merge the questions if required. \$\endgroup\$
    – Randomblue
    Oct 30, 2012 at 10:30
  • \$\begingroup\$ I think it's enough to make the questions different. I don't know SystemVerilog too, but someone might find that it needs a new tag \$\endgroup\$
    – clabacchio
    Oct 30, 2012 at 10:33
  • \$\begingroup\$ Ok. I will retag the other question. \$\endgroup\$
    – Randomblue
    Oct 30, 2012 at 10:34
  • \$\begingroup\$ You could first ask on Meta if a new tag is needed :) \$\endgroup\$
    – clabacchio
    Oct 30, 2012 at 10:36

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If you are manipulating strings that is going to be faster to do on a microprocessor than in hardware. However, for FIX you aren't really dealing with strings so much as you are dealing with numbers. Sure the fields are ASCII but you need to convert a lot of them from ASCII to numbers to make any sense of them (e.g. volumes).

I'm not sure that there are any Verilog libraries that will help you with string manipulations but basically, a Verilog compiler can understand ASCII and convert it to its bit representation, e.g. see this answer to Assign ASCII character to wire in Verilog.

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