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In my book there is a question stated:

Can a memory chip of capacity 512 KB have the starting address 2B0000h?

To me this seems like an incomplete question with a wrong answer in the book. The answer states:

No, because the first 16 bits of the starting address are zero, which means the capacity of a chip that can have this starting address is 64 kB.

Is it possible to deduce such an answer based on the given information and why does he say that the capacity of a chip that can have this starting address is 64kB, if the one writing the answer wrote 64kb I would understand that he got it from the 16 zero bits, but even then we can't know if there are more chips and a decoder before it all enabling different chips or if there are more of these chips connected in parallel to form 16 bit words etc.? Also we don't even know how many bits we need for offset, as we don't know if the word on for this processor is 8, 16, 32 bit etc. or if it can address only words or bytes?

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    \$\begingroup\$ I think this question should be related to some topology given previously in the book. It does not make much sense without context or extra information. \$\endgroup\$
    – Eugene Sh.
    Nov 19, 2019 at 21:31
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    \$\begingroup\$ I agree, both the question and answer are odd without specific context. In theory a chip could have any logical starting address. If it's an independent chip, why would the first address be anything but zero? \$\endgroup\$
    – Anders Petersson
    Nov 19, 2019 at 21:32
  • \$\begingroup\$ @Eugene Sh The previous topics covered are designing chips 16x8 from 16x4 etc. and ram, rom, cache, and then there are examples like this asking questions without knowing what exactly they refer to. The other questions even without answers seem fine so I was thinking there is a trick in this one which I don't understand . \$\endgroup\$
    – user1949350
    Nov 19, 2019 at 21:38
  • \$\begingroup\$ I would think that it should be related to some topology where the memory is organized in banks and composed of several chips. Then a portion of address will go on the CS lines and then such a question might make sense. \$\endgroup\$
    – Eugene Sh.
    Nov 19, 2019 at 21:39
  • \$\begingroup\$ The other questions usually state, there is a block 1024x32bit composed of 512x16bit memory chips so it's possible to deduce how many CS lines you need etc. and I understand that, but I was thinking maybe from the leading 2B there was a slight chance it's somehow possible to deduce the number of CS lines etc. so I thought I'd ask just in case. \$\endgroup\$
    – user1949350
    Nov 19, 2019 at 21:44

1 Answer 1

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The question makes perfect sense in context of how things are kept simple in an usual textbook. There are no MMUs or other fancy base address selectors, it's just how to match a bit pattern on bus and decode it to a chip select for large enough a block of memory.

The memory is said to be 512 kilobytes (0x80000) and can be assumed to be byte addressable in one contiguous chunk with single chip select for simple address decoding. That chip then needs 19 bits of address lines to access all its addresses from 0x00000 to 0x7FFFF. Therefore any address decoding must use the remaining higher address bits, so chip base address must be any multiple of 0x80000, including 0, so for example 0x200000, 0x280000, or 0x30000 could be start addresses, but 0x2B0000 can't.

Address 0x2B0000 as start address must use address bit 16 and higher for decoding so it leaves address bits 0 to 15 for the chip so 16 address bits means 64 kilobytes is maximum block for a memory that must start at 0x2B0000.

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  • \$\begingroup\$ I understand that, but I could construct the memory in such a way that 0x2B0000 is the starting address and then the lower 16 bits can indeed address only 64kB but then I just start again from 0x2C0000 and then 0x2D0000 and so on, the starting address of the memory is still 0x2B0000. Please correct me if I am misunderstanding something. \$\endgroup\$
    – user1949350
    Nov 19, 2019 at 23:45
  • \$\begingroup\$ In theory you could do that of course, but in practice it could be quite complex and time consuming task which is not worth it. Most likely has not been discussed in the class for a reason. Why map the memory to a difficult address when it is simpler to decode to an easy address? Please describe how would you actually connect it as eight separate 64 kilobyte blocks? At least draw a truth table. You'd need to convert at least 5 address bits into 3 address bits and the chip select. \$\endgroup\$
    – Justme
    Nov 20, 2019 at 0:24
  • \$\begingroup\$ Here you go: ibb.co/5LyWZLz \$\endgroup\$
    – user1949350
    Nov 20, 2019 at 1:23
  • \$\begingroup\$ It is still missing the chip select, but something along those lines, or slabbing a ROM or some kind of PLD there, so it is possible in theory. And it was not the point of the exercise given, it was to understand easy address decoding tricks, not to brute-force it. At some point real world limitations start to kick in. PCB real estate being too big, delays through logic gates end up too long, cost of chips too high to be able to sell at intended price, etc. I never said it is impossible. I just meant that in practice nobody would decide to actually implement it after seeing it on paper. \$\endgroup\$
    – Justme
    Nov 20, 2019 at 1:46
  • \$\begingroup\$ Yes, I understand. I'm just saying that it's possible and that's why the "can you make it" questions confused me. In my opinion a better starting address for this example would have been 0xfe0000 so at least then if you want to brute force it you have to assume that there is nothing on 0x00xxxx. Anyway, I am going to accept your answer as it gave me insight why someone might say you "cannot" make it. \$\endgroup\$
    – user1949350
    Nov 20, 2019 at 1:55

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