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I'm trying to understand the chip selects for some hardware I'm reverse engineering. There are more devices than CPU chip select lines so they are multiplexed using a variety of other inputs, including certain address lines being high/low.

The multiplexer I'm trying to figure out is a 2 to 4 output one (Toshiba TC74VHCT139AFT)

If it is 2 to 4, why are there 3 inputs A, B, and ~G?

Also, the truth table mentions active low G and the 4 outputs Y0-Y3. I've attached a pic of the truth table. The schematic I'm looking at shows inverters for those pins (also posted an image).

Do the inverters in the diagram mean that the signal is flipped on its way in/out? Or is this just a reflection of how the chip behaves? Based on how things behave, it seems to be the latter, but it's confusing. The CS lines out of the chip are active low as well.

Am I reading the truth table correctly that I'm looking for one of the Y outputs to go low to show it is "selected"?

in circuit truth table

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The 74xx139 is a decoder or demultiplexer, not a multiplexer.

The part contains two, 2->4 line decoders.

For each decoder, the A and B inputs select which of the four outputs will be Low when the Enable/Gate input is low. When the Gate input is High, no outputs will be Low.

The circles on the inputs or outputs of a logic IC indicate that that signal is "Active Low" - a logic Low indicates that the signal is Active.

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