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It says everywhere that a LIN network can be made up of at most 16 nodes (1 master node and up to 15 slave nodes). The id field however is 6 bits long allowing for more than 15 slaves to be addressed. Why this limitation to a total of 16 nodes? What was to happen if i were to add a 17th node?

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    \$\begingroup\$ There are 64 IDs. ID 0-31 uses 2 data bytes, ID 32-47 uses 4 data bytes, ID 48-63 uses 8 data bytes (with ID 60-61 for diagnostics and 62-63 being "reserved") As I understand it, anyway. (Starting with LIN 2.0, anyway.) \$\endgroup\$ – jonk Nov 20 '19 at 6:35
  • \$\begingroup\$ The whole purpose of LIN was always to be a cheapa** version of CAN. If you have that many nodes, you should most likely be using CAN instead. \$\endgroup\$ – Lundin Nov 20 '19 at 12:35
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If a certain allowed resistance and capacitance is specified for each slave node, and 15 slaves is allowed for total resistance and capacitance on bus for error-free operation with good margin, then adding yet another node can exceed the total allowed resistance and capacitance on bus and then it fails to operate within specification as there is too much resistive and capacitive load.

On the other hand, if all slaves load the bus as little as possible, it might work fine with one more slave, or ten more, but that's why there are specifications. If the whole system and each device on it is made by the specification, it is safe to assume it works. Having an ambiguous specification which says you can have as many devices as long as the total bus load, rise times etc are not exceeded, it would be difficult to calculate beforehand how many devices you can have there, and it would need to be measured if the electrical parameters are within specification and good margins.

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  • \$\begingroup\$ I see. It just struck me as odd that the limit was so low, and also such a nice number that happens to be a power of 2. I would have thought they would have been able to engineer the resistances and capacitances up to a higher limit. Thanks. \$\endgroup\$ – Raul Grigorașcu Nov 20 '19 at 7:22
  • \$\begingroup\$ the IC designers had performance requirements to meet, such as total power dissipation (resistance) and ESD performance (capacitance). \$\endgroup\$ – analogsystemsrf Nov 20 '19 at 7:52

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