Need of External Pull Up/Pull Down for Processor I/O pins

Question

For a particular I/O pin, its been mentioned in the processor data manual that there is Internal pull down, after power on reset, in the device with a default drive state of the pin as tristate(Z).

I understand that when the processor drive state for that particular pin, when it acts as output(processor is driving), is in tristate, the internal pull down will be effective.

What happens when that processor pin acts as input and the state of the signal driven by an external device(say FPGA/Memory) is in tristate? Will this internal pull down be effective?

I confused myself with which one of these two is dominant.. Active(state of signal from external device) or passive(internal pull down)..

My question is, do I need a External pull up/down for that signal, taking into consideration that current will flow in low resistance path..

I suppose the Internal pull down is sufficient to get rid of that tristate.. Just wanted to check with you guys..

Thanks in advance..

Answer 1

It depends on the other device. If the other device is very high impedance then yes, the pull down will be effective.

But it depends on the values of things. If you know the values for things then you can solve for them.

It's best not to think in terms of "current will flow in low resistance path" and rather in terms of Ohms law (and voltage/current dividers). If you have two resistances that are about the same, then the voltage between them will be about half (if they are in series) and each will get about the same amount of current (if they are in parallel). Note that even if one is a little less than the other, all of the current doesn't just take that path. They still divide it about evenly.

So to with your pulldown. If the other end has a pullup that is about the same, your node will float to about the middle.

If you are designing a PCB then just add the pull down. You can always decide later not to populate it.