For a particular I/O pin, its been mentioned in the processor data manual that there is Internal pull down, after power on reset, in the device with a default drive state of the pin as tristate(Z).
I understand that when the processor drive state for that particular pin, when it acts as output(processor is driving), is in tristate, the internal pull down will be effective.
What happens when that processor pin acts as input and the state of the signal driven by an external device(say FPGA/Memory) is in tristate? Will this internal pull down be effective?
I confused myself with which one of these two is dominant.. Active(state of signal from external device) or passive(internal pull down)..
My question is, do I need a External pull up/down for that signal, taking into consideration that current will flow in low resistance path..
I suppose the Internal pull down is sufficient to get rid of that tristate.. Just wanted to check with you guys..
Thanks in advance..