I've been trying to implement a 32-bit adder by instantiating two 16-bit adders. The code is compiling but failing some test cases. I don't know what is going wrong in this.

# verilog code

module top_module(
input [0:31] a,
input [0:31] b,
output [0:31] sum);
endmodule


This is the top level figure of the circuit:

This is the output waveform:

• Hint: your adder block should have a carry_out output and a carry_in input. – The Photon Nov 20 '19 at 21:43
• @ThePhoton can you please tell me how I can instantiate the cin and cout by looking at the above figure. – animad93 Nov 20 '19 at 22:19
• @animad93 no, that'd really rob you of any chance to learn. – Marcus Müller Nov 20 '19 at 22:40
• @MarcusMüller. Okay – animad93 Nov 20 '19 at 22:41
• @animad93, you'd need to change the definition of the add16 module. – The Photon Nov 21 '19 at 0:18