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I've been trying to implement a 32-bit adder by instantiating two 16-bit adders. The code is compiling but failing some test cases. I don't know what is going wrong in this.

verilog code

module top_module(
    input [0:31] a,
    input [0:31] b,
    output [0:31] sum);
    add16 adder2 (.sum(sum[16:31]), .a(a[16:31]), .b(b[16:31]));
    add16 adder1 (.sum(sum[0:15]), .a(a[0:15]), .b(b[0:15]));
endmodule

This is the top level figure of the circuit:

block diagram

This is the output waveform:

timing diagram

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  • 5
    \$\begingroup\$ Hint: your adder block should have a carry_out output and a carry_in input. \$\endgroup\$ – The Photon Nov 20 '19 at 21:43
  • \$\begingroup\$ @ThePhoton can you please tell me how I can instantiate the cin and cout by looking at the above figure. \$\endgroup\$ – animad93 Nov 20 '19 at 22:19
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    \$\begingroup\$ @animad93 no, that'd really rob you of any chance to learn. \$\endgroup\$ – Marcus Müller Nov 20 '19 at 22:40
  • \$\begingroup\$ @MarcusMüller. Okay \$\endgroup\$ – animad93 Nov 20 '19 at 22:41
  • \$\begingroup\$ @animad93, you'd need to change the definition of the add16 module. \$\endgroup\$ – The Photon Nov 21 '19 at 0:18
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To chain smaller adders to make larger ones, you need the building-block adders to have carry in and carry out connections and you need to link those connections from one ader to the next.

Your diagram does not match your code, your diagram shows a carry connection, but your code does not.

You need to expand your add16 module to support carry in and out connections if it does not already do so, then connect them up as in the diagram you have drawn.

P.S. This is the sort of thing you would normally only do as an excercise, normally you just use the + operator to add things and let the synthesis tool sort it out.

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