I'm considering using this zero-cross detector circuit in a design but I'm struggling to understand exactly how Q1 is activated. The description says "Q1 turns on and feeds current from C1 to the opto via R4, whenever the mains voltage (divided by (R1+R2)/R3) is lower than the voltage across C1." I understand this, but it doesn't explain how the gate of Q1 is activated. In order for the optocoupler to indicate a zero crossing, the gate must be activated only when a zero-crossing occurs, so its reasonable to assume that it has something to do with the capacitor discharging, but how it actually happens is still eluding me. Can anyone venture an answer?
D1-D4 form a bridge rectifier that will charge C1 up to about 1/20th of the peak voltage of the incoming AC power. (R1 + R2 are 440K, R3 is 22k 440/22 = 1/20).
During this time that C1 is charging the current will flow through C1 and through D5. This will reverse bias the base emitter junction of Q1 so it will not pass any current.
For a short period at the the end of each 1/2 cycle of the incoming AC the voltage will will drop to a low value and C1 will start discharging into R3 via the base emitter junction of Q1. (The emitter will be negative with respect to the base). This in turn will cause a pulse of current to flow in the collector of Q1 through the optocoupler LED from C1 (which is still charged at this time).
The pulse of current will cause the output transistor of the opto-coupler to draw current and cause the output voltage to pulse to ground for a short time (500us-1ms).
These pulses will be centred on the zero-crossings of the input signal.
I am learning electronics myself and Kevin's answer confused me to the point where I was wondering what I was misunderstanding about the circuit, so I simulated it and found that my initial instincts and node analysis were actually correct. I will explain:
The following is my copy of your circuit in LTSpice, ignoring the isolation aspect, which should be straightforward, and is not what the question is about.
My understanding is as follows:
R2 serve primarily to limit the current from mains (120/240VAC).
C1 is a bypass capacitor that serves to smooth the input to the rest of the circuit.
D1 D2 D3 D4 form a full wave bridge rectifier. This normally functions to rectify an AC voltage source into DC, but in this circuit the values of the resistors and capacitors have been specially selected to perform a different function; zero cross detection.
R3 serves to control the voltage at
Vin, the south end of this resistor can be thought of as ground.
C2 is a carefully chosen capacitor that would normally serve as the smoothing capacitor for the bridge rectifier, but in this circuit it's value in combination with resistor
R4 control various properties of the zero crossing 'signal'.
Here is the input signal and
Vin superimposed. Note that when the input signal nears zero
Vin is pulled low. This is the effect of the transistor going into its active region (explained below) and providing a path for the energy stored in the
C2 to discharge through
Note: I've done some math to superimpose
Vin over the AC input signal so the output is clearer.
So the simulation seems to show the circuit functioning as desired.
How it works is a bit tricky, or at least I think so.
The following is
The effect of adding a diode at the cathode of
C2 basically subtracts the peak voltage and then adds the diode voltage drop.
Ve can actually go negative. This is the key to understanding the behavior of this circuit.
The following is a plot of
Ve and the current through
Ve is going positive it hits a ceiling of 500mv or so. This is because 0.5V is the voltage in which the diode is forward biased and acts as a low resistance path to to ground. The voltage at
Ve will remain at 0.5V because the capacitor is charged.
Ve can go negative in reference to ground and the base of
Q1 is ground,
Q1 is positive which as we know will put the transistor into its active region and allow current to flow from
As the AC input nears zero
C2 will drain through
R3 until the voltage at
Ve reaches -0.7V, and
Q1 will become active as now
Vbe is 0.7V. This creates a low impedance path for the remaining energy in
C2 and the rest of the low input current to flow through
R4 and the optocoupler (in your circuit).
This low resistance path is only available until the voltage at
Vin rises to the point where the capacitor recharges and cuts off the transistor.
Here's a plot of
Vin and the current through
Some more notes:
In order to keep power consumption as low as possible (for an application running 24/7), I increased R1 and R2 to 560 kOhms each, and R3 to 33 kOhms. I further increased R4 to 2k2, and for Q1 I used a BC517 Darlington type. As optocoupler, I used a 4N35, as recommended.
This worked quite well, but I also wanted to keep impulses short (for firing a triac, I did not want accept impulse width of 1 ms, which I expected to fire the triac too early). For this purpose, I inserted a 5V1 zener diode in the base line of the transistor, and in order to diminish leakage current through the zener diode (before 5V1 is reached), I added a 100 kOhm resistor between base and emitter of the BC517. This procedure reduced the impulse width to about 200 microseconds.
Then I controlled for the phase of the detected zerocross relative to the actual mains zerocross. I found that the impulse was not centered around the actual zerocross (as expected) but just started with zerocross. This means, the impulse comes with some delay. I suppose that the 1nF capacitor C2 (which was 820pF in my case, because I only had this one at hand) causes delay, which becomes more pronounced with my increased resistors. I did some calculations on this, which I do not paste in here, but they supported the idea that C2 tends to delay the impulse. I was fine with a detector with the detection impulse starting right with the actual zerocross.
I am sorry for not providing a circuit after all these changes, but I do not have the software for that. I wanted to share my experience because it includes (a) saving power, (b) decreasing impulse width, (c) delaying impulse onset.