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Here is a NOR based SR latch: nor sr latch And here is a NAND based SR latch:
nand sl latch

So, basically first we flipped the orientation of R and S and then declare that in our NAND latch, the output would be flipped i.e. 0 for set and 1 for reset which defies the meaning of set and reset.

Why in the first place did we change the names of the input corresponding to Q only to find out it reverses our output ?
Had we kept the RS naming in both the latches, we would be getting a sensical output that would be 1 for Set regardless of NAND or NOR gates used.

PS: I don't know if this question belongs to this stackexchange as it focuses on why a decision was made. Please move to proper site if required.

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  • \$\begingroup\$ I suggest you make the truth table of the NAND SR too and put it side-by-side with the NOR version. \$\endgroup\$
    – Oldfart
    Nov 22 '19 at 2:28
  • \$\begingroup\$ I'm not sure I understand the question. Are you asking why in the NAND latch they didn't swap the label S' with the label R, and why they didn't swap the label R' with the label S so that it more resembles the NOR latch? \$\endgroup\$
    – serpixo
    Nov 22 '19 at 2:49
  • \$\begingroup\$ I view a NOR gate as having this behavior "Any 1 in gves a 0 out" while the NAND gate behaves as "Any 0 in gives a 1 out.". You will notice these behaviors are inverted. \$\endgroup\$ Nov 22 '19 at 3:07
  • \$\begingroup\$ @serpixo I'm asking why did they make the swap the letters at all ? Try NAND and NOR latch with R corresponding to Q both the times, you'll get the same truth table. Simple. Useable. Sensical. \$\endgroup\$
    – Hritik
    Nov 22 '19 at 18:22
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Choice of what represents SET or RST in either circuit is really somewhat arbitrary and and up to the designer to choose.

It is a relatively good idea to use the strategy that you suggested and have the SET input be the one that makes the Q output go to a '1'. I can see no reason why you would do it differently unless that was some design choice in a particular circuit to do so.

In the end I would not spend too much time trying to figure out the original motivation as long as you understand how both latches work.

On a final note you may want to consider drawing the dual NAND gate SR Latch with the DeMorgan equivalent gate symbols in that it makes it a lot easier to visualize the logic operation.

enter image description here

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  • \$\begingroup\$ I do share your opinion and I do understand how both the latches work, I'm just curios why the people who named latch named them RS Latch (NOR) and SR latch (NAND). Why not call both of them RS Latch and have the same truth table, have consistency and be done with it. \$\endgroup\$
    – Hritik
    Nov 22 '19 at 18:27
  • \$\begingroup\$ @Hritik Those names are not official or standard. Either name could be used for a NOR latch and either name could be used for a NAND latch. \$\endgroup\$ Nov 22 '19 at 18:53
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Here is the truth tables

SR NOR latch
S  R      Q Q'
0  0      no change from previous values
0  1      0 1
1  0      1 0
1  1      undefined behavior


SR NAND latch
S' R'     Q Q'
0  0      undefined behavior
0  1      1 0
1  0      0 1
1  1      no change from previous values

"New latch"
SR NAND latch with S' replaced with R and R' replaced with S
S  R      Q Q'
0  0      undefined behavior
1  0      1 0
0  1      0 1
1  1      no change from previous values

So, with reference to the last truth table you can see how it is different from SR NOR latch. In particular, if I'm designing with your new latch, how should i have the latch keep its previous value? Intuitively, I would want to keep Set and Rst low. But with your Latch, this gives me undefined behavior.

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