Just as the title says, how does this occur? I'm trying to wrap my head around processes vs components and I don't understand how this mechanism works. This may not be a proper question so please help me formulate it to be more specific, but I just really need to understand this concept to keep moving forward in my design.
count: process (x) variable cnt : integer := -1; begin cnt:=cnt+1; if (cnt > '9') then cnt:=0; OVERFLOW <= '1'; endif; end process;
I understand that the if statement is dependent on the previous increment statement. I also understand why order is important (logically it makes sense - I check condition after updating), but what doesn't make sense to me is without any kind of clocking or other sequential mechanism, how does OVERFLOW (which is a signal in this example, not shown) get it's value updated concurrently with all the other signals in the design when it depends on cnt being updated first? Furthermore, any other signals which have implied processes associated with OVERFLOW are assigned concurrently, making them dependent on cnt by proxy as well.