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I'm a High School senior. Our new teacher doesn't teach well at all and we have a test this Thursday.

I don't know which gate to use with the counter(with JK flip-flops) to reset it. Or to set it(To return it to 1 I mean)

As example:

We have a counter(Async) that counts from 0 to 15. It's gonna use 4 flip-flops(Obviously) and when it almost reaches 16 it becomes 0. But I don't know which logic gate I use to do that(NAND or AND or OR or NOR or XOR or what!?)

And we have a counter(Async) that counts from 15 to 0. It's gonna use 4 flip-flops(Obviously) I want it to start from 15. This means I will have to set some flip-flops but the problem is that which logic gate I use to do that(NAND or AND or OR or NOR or XOR or what!?)

Also, it uses "Init" which I don't know what it does mean.

Please help, I have a test soon and sorry for my English(I'm not an English-native speaker)

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  • \$\begingroup\$ A 4 bit binary counter going from 0 to 15 will naturally roll over back to 0 at the next clock so no reset necessary. To start at a specific value (0 and maximum count are easiest) you will need to CLR (start at 0) or Preset (start at max count) all the flip flops prior to starting the count sequence. \$\endgroup\$ – Peter Smith Nov 23 '19 at 16:26
  • \$\begingroup\$ Start with a clear "spec" such as a truth "state" table. You can use gates to detect any count value to reset or set or detect an end of count then preset. It depends what you want to do. An Async counter means cascade like /2/2/2/2 = /16. Sync counter means common clock. e.g. programmable counter can use binary wheel to count down or up. and inverted output makes an upcounter look like its counting down \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 23 '19 at 16:59
  • \$\begingroup\$ But as Peter says no gates needed for 0 to 15 repeating except for the init(ialization of a preset value=N) e.g. if QaQbQcQd=1111 then init or preset some value for an up counter or =0000 then init for a down counter makes it a programmable counter of divide by N or /16-N depending if up or down \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Nov 23 '19 at 17:02
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something like this will recognize a pattern

schematic

simulate this circuit – Schematic created using CircuitLab

You may get glitches out of this circuit, because the aynch counter outputs (those 4) may not all change at exactly the same nanosecond.

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