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LT1510 is a battery charger IC that can be configured to charge any kind of battery pack, I am interrested about the circuit given in the application note referenced AN68F page 24/36. The IC is used a Li-Ion battery charger. I want to understand the circuit around the OP AMP U2, and how U2 reset U3 (circled in red).

  • My first question, what is the role of C9, a capacitor that is connected between the inverting and non-inverting pin of U2 ?

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From the application note, I understood that U2 takes effect in the final stage of charging (Constant voltage charging). It says:

When the LT1510 is charging, U2 compares the voltage across the LT1510 internal 0.2ohm sense resistor to the voltage across R7. When the voltage across the sense resistor is lower than the voltage across R7 (or, alternatively, when the charge current drops below 75mA), U2’s output voltage drops. When U2’s output voltage drops, U2 latches at low state via CR5. U2’s output is connected to the RESET pin of U3.

  • What is the voltage across R7 ? I am not sure, but I think, first R7 with R8 and R9 make a voltge divider of VBAT+VRsense (VBAT is the battery voltage and VRsense is the voltage across the internal sense resistor).

  • How does U2 compares between VRsens and VR7 ? (the inverting input of U2 is connected to the battery pack and the non-inverting input is connected to a voltage divider )

  • U2 output is connected to VIN through R10, so how does this output latches at low state via the diode CR5?

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  • \$\begingroup\$ C9 comment added to answer - removes triggering on "noise" such as power supply charging pulses. \$\endgroup\$
    – Russell McMahon
    Nov 24 '19 at 20:37
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Warning:

Despite this being an LT application note, this circuit is not "fit for purpose". As an example of various techniques it does a good job. As a practical solution to a real world problem it would be a bad choice to use. As described below:

  • U3's function is unnecessary and will damage batteries through overcharging in real world applications.

  • U2 is a majestic device but is overspecified in this application and liable to cause stability problems due both to it's high performance and to the application notes failure to address these factors adequately.

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To make sense of the description it helps to refer to the LT1510 internal block diagram - seen here.
The portions of especial relevance are marked in green.

First, a few "notes":

  • RS1 is the 0.2 Ohm sense resistor referred to in the text.
    When connections to or around an IC "do not make sense" it often helps to refer to the device's internal connection diagram. You will find that the positive ends of R7 and internal RS1 are connected, allowing their relative voltage drops to be compared.

  • C9 in the application note is across the comparator inputs and serves to remove high frequency variations to stop the comparator triggering on noise. The time constant of R6, R7, C1 is about 100 μs - rejection of current variations due to the switch mode converter charging cycles is quite likely a major consideration.

    Making the super sensitive comparator sit down and not oscillate due to stray capacitance is probably another.

  • U2 output is connected to VIN through R10, so how does this output latches at low state via the diode CR5 ?

    The LT1011 datasheet here is an "open collector" comparator and requires an output pullup load. R10 serves that role.

    The question re output latching is essentially undelated to R10 and is described below.

    The LT1011 is a superb device and it's attributes are well suited to demanding high speed applications - but it is vastly overspecified for this role and will probably cause problems if used as shown here without extra components. Layout is critical, and specific supply bypassing and balance pin bypassing (none of which is shown in the application note example) is a very good idea indeed. It has a gain bandwidth product of over 10 GHz (!) and is liable to "burst into song" under any provocation. The datasheet describes precautions which should be taken to prevent this, but, using something more usual and far cheaper would be a better solution. (Sometimes application note writers like to use fancy components to 'strut their stuff' or sell ICs or ...? - this is an example.

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Battery charging current enters the "sense" pin, passes through RS1 and goes to the battery via the "battery" pin.

Battery charging is terminated when charge current falls below some preset value Iterm (say).
When this occurs the voltage across RS1 due to charging current falls below V= IR = Iterm/Rs1.
U2 acts as a comparator, comparing the voltage across RS1 (due to charging current) with the voltage across R7 (which sets the charge terminate threshold).

The "high ends of RS1 and R7 are commoned at "sense"
and the drop across R7 is R7/(R7+R8+R9) x Vbat.
Which here = 2k2/(2k2+560k+430k) x Vbat = 2.2/992.2 x Vbat
= 0.00222 x Vbat = Vbat/451 (!)

At end of charge when the comparator switches the voltage across R7 is equal to the voltage across RS1
= Ichg x 0.2 Ohm = Iterm x 0.2
SO Vbat/451 = Iterm x 0.2 or
Iterm = Vbat/90.2

For 2 cell LiIon and Vbat_term = 2 x 4.2V = 8.4V
Iterm = 8.4/90.2 = 93 mA.
Without looking through the text for the battery capacity, that would be slightly less than C/10 for a 1000 mAh battery - which is "Road Warrior" level charging.
Or about C/2 for a 200 mAh, or C/5.4 for a 500 mAh battery - which would be conservative and well charged levels respectively.

Finally, once the comparator switches, U2 output goes low, CR5 conducts and the R 7 8 9 divider is driven low taking the non-inverting input 'very low' thus latching the end of charge state.

E&OE. ie there MAY be a numerical mistake in there somewhere, as happens, but the principle applies.

NOW, I will read the app note text ... :-)

OK - correct as far as I went. AFTER the comparator trips the timer at right (U3) adds an extra period of top up. I consider that this would be VERY inadvisable and it violates just about every (maybe every) CCCV charging application I have ever seen (and I've seen a few).
They say the trip point is 50 to 100 mA so my 93 mA lies in that range.

I'd say the circuit was overly OK albeit a little complex if you left off the U3 circuitry, and that adding U3 is not only overkill but is literally battery killing. Just because it's in an app note from a superb manufacturer doesn't make it right, alas. If it was by one of the now dead great names I'd go and have another look at my reasoning but as it is by 'application engineering staff". I'd suggest that in this case they got too enthused in demonstrating a useful idea. The app note is dated 1996 - the above applied to LiIon cells of that date and to the latest ones now - with a slight increase in the CV voltage for some of the very latest cells.

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  • \$\begingroup\$ What about C9? What is the rôle of this capacitor places between the inputs of the OPAMP? \$\endgroup\$ Nov 24 '19 at 18:37
  • \$\begingroup\$ When you said: "The "high ends of RS1 and R7 are commoned at "sense" and the drop across R7 is R7/(R7+R8+R9) x Vbat." you have just neglected the voltge drop across Rs1, right ? because of its low value \$\endgroup\$ Nov 30 '19 at 20:03
  • \$\begingroup\$ @luxinapado NO! - the difference is crucial. Note that R7 connects to the sense pin. Now look at fig 2 which I have copied in my answer - The "top" of RS1 also connects to sense. The top ends of both are HARD CONNECTED. So the voltage at the BOTTOM / BAT pin side of RS1 is lower than SENSE due to current flow, and the voltage at the BOTTOM (lower V side) of R7 is lower due to the R7 8 9 divider action. The R7 voltage sets a negative reference relative to sense that V_RS1 must be BELOW for charging to continue. \$\endgroup\$
    – Russell McMahon
    Nov 30 '19 at 20:27
  • \$\begingroup\$ || NBNBNB - the circuit is not a good one to copy, as I say elsewhere. The timer is both unneeded and damaging and the comparator could be a cheap lower spec one. \$\endgroup\$
    – Russell McMahon
    Nov 30 '19 at 20:27
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When you said: "The "high ends of RS1 and R7 are commoned at "sense" and the drop across R7 is R7/(R7+R8+R9) x Vbat." you have just neglected the voltge drop across Rs1, right ? because of its low value.

NO! - the difference is crucial.

Note that R7 connects to the sense pin.
Now look at fig 2 which I have copied in my answer AND THE ANNOTATED DETAIL BELOW

The "top" of RS1 also connects to sense.
The top ends of both are HARD CONNECTED.
So the voltage at the BOTTOM / BAT pin side of RS1 is lower than SENSE due to current flow,
and the voltage at the BOTTOM (lower V side) of R7 is lower due to the R7 8 9 divider action.

The R7 voltage sets a negative reference relative to sense that V_RS1 must be BELOW for charging to continue.

NBNBNB - the circuit is not a good one to copy, as I say elsewhere. The timer is both unneeded and damaging and the comparator could be a cheap lower spec one. –

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  • \$\begingroup\$ What confused me in the fomula R7/(R7+R8+R9) x Vbat, is the use of VBAT, I think this is right only when the comparator switches off (V+ = V-), but while charging with "High" currents (Let's say 1C or C/2), we cannot apply this fomula cannot be applied to compute VR7. right ? \$\endgroup\$ Dec 22 '19 at 21:29

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