# Why does a rise in ambient temperature cause a base-voltage-biased grounded emitter stage to saturate?

This is actually exercise 2.9 in Horrowitz and Hill 2nd Ed. which is posed as:

Verify that an $$\8 ^\circ C\$$ rise in ambient temperature will cause a base-voltage-biased grounded emitter stage to saturate, assuming that it was initially biased for $$\V_C = 0.5 V_{CC}\$$.

The section it appears in is talking about the shortcomings of the single-stage grounded emitter amplifier, and mentions three deficiencies:

(1) non-linearity such that the gain varies from 0 to a (negative) maximum due to the lack of an external resistor on the emitter

(2) a variation in input impedance $$\Z_{in} = h_{fe}r_e = 25 h_{fe} / I_C\$$ (for $$\I_C\$$ measured in mA and the 25 is 25mV which is an estimate for $$\V_T\$$ in the Ebers-Moll equation, $$\h_{fe}\$$ is the gain and $$\r_e\$$ is the internal resistance)

(3) the effect of temperature on biasing according to which $$\V_{BE}\$$ varies by about 2.1mV / $$\^\circ C\$$ for fixed $$\I_C\$$. Apparently $$\I_S\$$ (the saturation current of the transistor) is roughly proportional to $$\1/T\$$, such that for fixed $$\V_{BE}\$$ the collector current $$\I_C\$$ increases by a factor of 10 for a 30$$\^\circ\$$ rise in temperature.

It feels like the answer to the question is a trivial consequence of (3), but I'm struggling due to not really understanding the conditions of transistor saturation, and how the $$\8^\circ\$$ rise in temperature can cause saturation regardless of $$\V_{CC}\$$.

• Please add a schematic, showing resistor values. – Dwayne Reid Nov 23 '19 at 20:56
• @DwayneReid It's an NPN BJT, emitter grounded, $10\:\text{k}\Omega$ resistor in the collector leg with a $+20\:\text{V}$ rail, and a "DC coupled signal in" fed directly to an unbiased base. It's a very, very abstract circuit and the book is asking the reader to "think theoretically" about the topic using a couple of quantified "rules of thumb" to help out. The OP's question can be answered, in general. – jonk Nov 23 '19 at 21:06
• kikazaru, You have the book and there's lots of material there for you to slog through. Over time, these details will sort themselves out, if you keep at it. But I can disprove your assertion that (3) explains the others. The non-linearity being discussed in (1) has nothing whatever to do with the effect of temperature discussed in (3). Therefore, (3) does not explain (1). They are independent. In fact, (1) is entirely signal-dependent. Variations in the signal cause the gain change. If the signal doesn't change, the gain stays at one value. (2) is also an independent effect. – jonk Nov 23 '19 at 21:09

3) fixed Vbe and the collector current Ic increases by a factor of 10 for a 30∘C rise in temperature.

If 10x Ic occurs from 30'C rise so 8'C rise implies 8'C/30'C *10= 2.667x rise in current.

Given Vc=Vcc/2 Re=0 thus saturation is twice the current at Vce=0 , 8'C is sufficient.

If the transistor is biased at Vcc/2 then a doubling of Ic will cause it to saturate.

We know that $$\I_C= I_S[{e^{V_{BE/V_T}} -1]} \approx I_S[{e^{V_{BE/V_T}} ]}\$$ Near room temperature, Vt is about 25.3mV, so Ic will double for a change in Vbe of $$\\ln(2)V_T\$$ = 18mV.

That is equivalent to a temperature change of about +9°C.

For a given fixed bias voltage, any junction increases its current with increasing temperature (same as saying: with fixed current, voltage drop decreases). If the junction is the B-E junction, and assuming a roughly constante hFE, Ic will increase by the same factor (or try to increase, if Vce doesn't reach saturation). For a given Vcc and Rcollector, there will be a junction temperature that will lower Vce up to the saturation value.