LTspice transformer voltage course problems at low duty cycle

Question

I am trying to simulate full bridge SMPS in LTspice where I can change the input voltage to the voltage regulator (LT317) by changing the pulse width of the PWM signal at the MOSFETs.

Everything works as expected at higher duty cycles (>20%), so the voltage on the transformer is positive when the 1st pair of MOSFETs is conducting and the voltage is negative when the 2nd pair of MOSFETs is conducting. Here is the schematic and plot for 80% duty cycle:

But when I change the duty cycle to the lower value the transformer seems to be "working" even if the transistors arent conducting.

Notice that the time base is the same.

And the same plot but enlarged:

Questions: Why is the transformer working when all of the transistors are not conducting?

How can I make the transformer work only when the MOSFETs are conducing?

This problem makes the voltage on the C2 condensator always the same (independent from the duty cycle).

Thanks in advance.

UPDATE(27.11.2019)

I've tried to solve this problem byt trying few things:

1. I thought that because of the MOSFET capacitance, inductance of the transformer and the resitance there was an RLC resonant circuit. I changed the values of the capactiances in the IRF740 model that I applied to the schematic.

.MODEL IRF740 VDMOS(KP=3.1089 RS=0.0048 RD=0.4166 RG=0.91 VTO=4.5
+LAMBDA=0.001 CGDMAX=1218p CGDMIN=15p CGS=1300p TT=533n
+IS=2.41E-09 N=1.401 RB=0.013053 m=0.452 Vj=0.36 Cjo=1424.39pF)
+mfg=STmicro Qg=35n Ron=0.48 Vds=400)

Changing the values didn't solve the problem.

2. I changed the circuit by removing the MOSFETs and replacing them with voltage controlled switches pararelled with diodes. That erased all the capacitance but there was no result that try either. In fact there were much more oscillations after switching.

So I returned to the MOSFETs.

3. After reading (this article)(http://ltwiki.org/index.php?title=Transformers) I've decided to change some of the inductors parameters (pararell capacitance, resistance and series resistance). It did change the voltage course on the transformer but still I am not satisfied with the results.

   3.1. For values of the inductor: R_series = 10m; R_pararell = 2; C_pararell = 10p (for the primary winding I've set the secondary winding parameters 100 times lower - 10:1 ratio); the oscilations where gone, but the peak voltage on the primary side of the transformer decreased from ~325 V to ~150 V.

Green is the transformer voltage, red and blue PWM to the mosfets.

3.2 When I changed the parameter values to more be "realistic" (R_pararell to 200 ohms on the primary winding, 2 ohm on the secondary) the peak voltage transformer went up to ~325 V, but there appeared one overvoltage, oscilation (I dont know how to call this). This time I think it looks "real" and the opposite polarized voltage peak is just because the energy stored in the inductance has to unload somehow (is that correct?).

I've applied the inductor (L = 200 uH) before the C2 (C2 = 100uF) capacitor. However the voltage on the capacitor never stopped rising.

The plots are for 10% duty cycle.

Is that because the way im driving MOSFETs is wrong due to what @Big6 wrote?

Where my approaches at least somehow correct?

@Big6 why only the lower transistors capacitances will be charged? Also according to Kirchoff's law even if they would be charged one would be charged to +Vp and the second one to -Vp so the voltage on the primary winding should be 0 V.

(here is the .asc file, I uploaded it to the google drive)[https://drive.google.com/file/d/1amOW-eyB5OYwljlaeMHK7lGp6Er8rYW8/view?usp=sharing]

Answer 1

A couple of things:

1. The transformer is there to provide the required step-down ratio but also to make the circuit isolated from the input side. If you notice, you've grounded the lower terminal of C2 (an all of the other legs there) on the secondary side of the transformer. So, in some way, that is interacting with what you have going on on the primary side and you don't have isolation.

2. As mentioned by Dave Tweed in his answer, if you really want to control the voltage based on the duty cycle, you need an LC fitler, which will, in theory, give you the DC component of your wave on the secondary. That should be D*Vs, where Vs is the peak voltage you get on the secondary. By just having a cap there for filtering, it will get charged up the peak value after some cycles.

I know that LTSpice will sometimes complain if you don't provide a ground reference point to compute the operating point, so one way people deal with transformers is by adding a connection to ground through a large resistor (100M, 1G). It would look like this:

See this

Notice the large isolation resistor on the secondary side.

One thing that you may not be seeing now but could be relevant later. When driving the MOSFETs, at low duty cycles, all the blanking (dead-time) you're introducing, may not work as expected. By that I mean, that at the output of the H-Bridge, you should ideally see a replica of the dead-time, that is, you should see: +V (lasts Ton), then 0V (lasts Tdead), and then -V(lasts Ton).

However the way you're driving the MOSFETs, you will see (for sure at light loads) +V and -V, with no dead time in between even when you do add the dead time in the driving signals. The reason being, without going into more details, is that at the dead time, all your MOSFETs are OFF, and the two lower ones have their drain-source capacitance charged up to either V+ and V- (at low light loads it takes a longer time to discharge them). So a better approach is to drive the two lower MOSFETS ON at the intended dead time (Two upper ones OFF), and that way you definitely guarantee that at the dead time, the output voltage of the H-Bridge is 0V. Then, with an appropriate filter (i.e L-C), you can get the desired DC output voltage on the secondary side of the transformer: \$N\cdot D\cdot V_P\$, where N is the turns ratio of the transformer, D is your duty cycle, and Vp the peak voltage of the square wave coming out of the H-Bridge. No dead time or very close to none means (in addition to shoot-through) that D approaches 1, so you don't have much control over the DC output voltage. So ideally you could change D (by inserting different dead times) and therefore get different DC output voltages.

Hope it helps.

QUESTION:

@Big6 why only the lower transistors capacitances will be charged? Also according to Kirchoff's law even if they would be charged one would be charged to +Vp and the second one to -Vp so the voltage on the primary winding should be 0 V.

You drive two transistors at a time (diagonally). There are two transistors off. It looks like this:

Reference

I hand drew the drain-source capacitances for each MOSFET. If you notice, the transistors you're driving, are shorting their capacitance and therefore the voltage across the capacitance is 0V during that interval. Take a look at the other two transistors that are off, the potential difference across their D-S capacitances, is about +V. Now what happens is that at the dead time, if all transistors are driven off, you don't necessarily get 0V across the bridge outputs, and that is because your bridge output is a differential measurement from the two lower drains (one is charged up to +V and the other is at 0V, so \$V_+-0V=+V\$). Unless you have some load, across the bridge output, during the dead time, nothing is actively discharging those caps. Under normal load conditions, you may not see it but under light loads, you can see it.

Take a look at this simulation of an h-bridge with no load attached:

I am driving those transistors similar to what you're doing, notice there is a 2\$\mu\$s dead time to avoid shoot-through. This is the output I get from the bridge under no load:

The 2\$\mu\$s dead-time I inserted at the input signal is not reflected at the output.

If I add a load (5\$\Omega\$), this is what it looks like:

You see the load is enough to discharge those capacitances quickly enough that I can see the dead time in the output. If I were to increase the load resistance, you notice how the dead-time is reflected at the output of the bridge but you see the round corners (like a cap would either charge or discharge):

Now you may ask why this is important. Well, the dead time, in addition to preventing shoot-through, also allows for having different pulse widths and therefore, after you rectify the output of the bridge, you should get all those pulses in the same quadrant and spaced as you wish. From there things are simple, after filtering, your DC output should be just the duty cycle times the peak voltage of the square wave.

If you drive the two lower transistors ON during the dead time, then for sure the nodes from where you take the output of the bridge, will be at the 0V, since any charge on those lower capacitances will be extracted. There are lots of important details here about timing, etc that I've omitted but just wanted to give you a general idea. One more advantage of turning those lower transistors ON is that current flowing through the inductance will have a somewhat easier path to flow at the dead-time, instead of just the upper MOSFET body diode.

Answer 2

That isn't how transformers work. Putting a fixed-voltage variable duty cycle signal on the primary will simply give you a fixed-voltage variable duty cycle signal on the secondary.

If you want to translate that secondary signal to a variable voltage, you'll need a completely different kind of filter between the transformer and the regulator.