# State Machine with D Flip Flops; how to deal with race conditions

Consider a state machine whose entire state is kept in a collection of edge-triggered D flip-flops. The outputs of these are fed into a combinatorial network which fully determines the next state, and is fed back into the flip-flops' inputs. On every pulse of the clock, the FSM transition states.

However, I am unsure about how to deal with races: on the positive edge of the clock, the flip-flops will propagate their inputs to their internal states (and outputs). Immediately, the outputs (through the combinatorial network) will change the flip-flops' inputs again. How is it guaranteed that the inputs are stable for long enough after the clock edge for the flip-flops to switch effectively?

I can think of two possible workarounds:

• Cascade two sets of flip-flops; this keeps the inputs stable, but would take two clock cycles to transition states.

• Use master-slave flip-flops. I am not sure whether this completely fixes the race, though: if the clock inverter (gating the "slave" flip flop) switches quickly (before the "master" flip flop" turns off), it could still result in unstable inputs.

How is this usually solved?

• Welcome to EE.SE.
– user105652
Commented Nov 25, 2019 at 0:45
• "By design". Look at the data sheets. Decide if there is a potential issue. There usually isn't. If there is, design it out. Commented Nov 25, 2019 at 3:10
• I have gone through some data sheets, but I am still a bit confused; e.g, SN74HCS72. To determine how long the inputs remain valid (assuming instantaneous combinatorial logic), I think I should be looking at propagation & transition delays. Both of these don’t have minimums; only typical and maximum delays. Follow-up question: if I build a master-slave FF out of discrete gates, how can I ensure that the “master” will turn off before the “slave” turns on, if there is no lower bound on the propagation delay for the clock inverter? Commented Nov 25, 2019 at 3:35

Edge-triggered FFs generally will not "beat" their own input setup and hold time requirements. You can usually string them directly together to form shift registers of arbitrary lengths.

Therefore, your concern is nothing to worry about. The only real issue in this setup is the maximum clock frequency, which is mostly determined by the longest path through the combinatorial logic.

• Yes. When all circuits are the same technology, I have never seen this be an issue. If you mixing old (slow) and new (fast) technologies, it can be an issue. Commented Nov 24, 2019 at 23:30
• Correct. Even if you have feedback there is a rigid order of progress.
– user105652
Commented Nov 25, 2019 at 0:43
• Thanks! Makes sense, I've seen plenty of designs that assume this, but I was wondering if there was something in the data-sheet I should be looking for to prove this. I come from the software world and analog matters scare me :) -- follow up question: if I build a master-slave FF out of discrete gates, how can I prove that the "master" will turn off before the "slave" turns on? What I'd want is a lower bound on the transition delay for the clock inverter, but that seems to be missing from all inverter data-sheets I've seen. Commented Nov 25, 2019 at 3:41

What you're describing is called a hold violation (zero-cycle hold violation, to be precise). Static Timing Analysis (STA) tools are designed to both detect and often automatically fix these violations. Techniques for fixing are numerous, some of the commonly used ones are

1. Resizing cells on the data path (see cell sizing)
2. Inserting an additional buffer cells on the data path