I'm getting started with Verilog, using FSM patterns. I'm finding that something I keep needing to do is to wait in a particular state until I see a leading edge of a (much slower) signal.
What I always end up doing is something like this:
module (... syncsignal input ...)
if (syncsignal && !oldsyncsignal)
state <= STATE_CONTINUE;
oldsyncsignal <= syncsignal;
I'm becoming less and less convinced this is a good idea, partly due to various edge cases (what happens if syncsignal goes high when I'm not in STATE_WAIT?), and partly because I haven't seen anything like it in other code I've seen.
This must be a requirement which comes up a lot. What's the standard way to do this?
I'm using the Warp dialect of Verilog for the Cypress PSoC devices.