# Doubt in SR Flip-flop

I am a beginner in digital logic. Please clarify me the following

In case of set condition with Qn=0, i am getting wrong answer Q_{n+1} and (Q_{n+1})' not complement to each other I am not able to find out where i made mistake. Kindly have a look at the following • If $S=1$ and $R=0$, your operation would be "SET", meaning that $Q_n=1$ .... Then your $Q_{n+1}=Q_n$ – KingDuken Nov 26 '19 at 18:26
• Maybe because your top right NAND has a 0 input, which would make it output 1. But you take that output to the lower NAND and say it's 0, which it isn't. – RaphaelP Nov 26 '19 at 18:30
• @RaphaelP sir in lower nand gate we give input Qn right? Is it Qn+1? Please correct me if i am wrong – Nascimento de Cos Nov 26 '19 at 19:04
• In fact my book it is written as for set - S=1, R=0, irrespective of Qn, output (Qn+1) will be 1. So i am checking what happens when Qn = 0 !!! For Qn =1 every thing is fine. – Nascimento de Cos Nov 26 '19 at 19:05
• Qn is the initial state. When the output changes, the cross coupling between the NAND gates must be reevaluated (for each gate, check it's inputs and write down the output). You'll notice that the Qn state is only relevant when neither S nor R are active (hold state). – RaphaelP Nov 26 '19 at 19:19 