I am a beginner in digital logic. Please clarify me the following

In case of set condition with Qn=0, i am getting wrong answer Q_{n+1} and (Q_{n+1})' not complement to each other I am not able to find out where i made mistake. Kindly have a look at the following

enter image description here

  • \$\begingroup\$ If \$S=1\$ and \$R=0\$, your operation would be "SET", meaning that \$Q_n=1\$ .... Then your \$Q_{n+1}=Q_n\$ \$\endgroup\$ – KingDuken Nov 26 '19 at 18:26
  • \$\begingroup\$ Maybe because your top right NAND has a 0 input, which would make it output 1. But you take that output to the lower NAND and say it's 0, which it isn't. \$\endgroup\$ – RaphaelP Nov 26 '19 at 18:30
  • \$\begingroup\$ @RaphaelP sir in lower nand gate we give input Qn right? Is it Qn+1? Please correct me if i am wrong \$\endgroup\$ – Nascimento de Cos Nov 26 '19 at 19:04
  • \$\begingroup\$ In fact my book it is written as for set - S=1, R=0, irrespective of Qn, output (Qn+1) will be 1. So i am checking what happens when Qn = 0 !!! For Qn =1 every thing is fine. \$\endgroup\$ – Nascimento de Cos Nov 26 '19 at 19:05
  • \$\begingroup\$ Qn is the initial state. When the output changes, the cross coupling between the NAND gates must be reevaluated (for each gate, check it's inputs and write down the output). You'll notice that the Qn state is only relevant when neither S nor R are active (hold state). \$\endgroup\$ – RaphaelP Nov 26 '19 at 19:19

Qn=0 has changed into Qn+1=1.
Once you propagate Qn+1 to the lower gate and reevaluate it's output, you'll see that there's no contradiction.


|improve this answer|||||
  • \$\begingroup\$ Sir set condition in that case exists only when Qn = 1. It is not so right? Qn = 0 --> invalid:? \$\endgroup\$ – Nascimento de Cos Nov 26 '19 at 19:35
  • \$\begingroup\$ "Set" makes Q become 1. If it's already 1 nothing happens, but there's nothing wrong about it. It's just like pressing a floor button on an elevator, you can "set" it as many times as you want. \$\endgroup\$ – RaphaelP Nov 26 '19 at 19:45
  • 1
    \$\begingroup\$ @NascimentodeCos to clarify, you would typically hold clock and S high long enough for the circuit to settle to a stable state, then bring clock low to hold that state. So even though initially that bottom right gate will see a 0 from Q, you would wait long enough for the next Q value of 1 to propagate to that gate. \$\endgroup\$ – serpixo Nov 26 '19 at 21:58

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.