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So I am writing a simple blinking LED Verilog code that will be run on a Cyclone10 LP (Device is called 10CL025YU256I7G) and will be tested on a Cyclone 10 Evaluation Kit (6XX-44504R-0D)

All code is written in Quartus Prime Lite 17.1

The link to Cyclone EK User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-c10-lp-eval-kit.pdf

The link To Cyclone EK Schematics: https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/cyclone10/c10lp-eval-a1-sch.PDF

Reference: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/cyclone-10-lp-evaluation-kit.html

The design module is

`timescale 1ns/1ns


module FPGA_Testing(input reset, input clk, output reg LED);

    reg [32:0] counter;
    reg state;


    always @ (posedge clk) begin
        if(reset == 1) begin
            counter <= 0;
            state <= 0;
        end
        else begin  
            counter <= counter + 1;
            state <= counter[20];
        end

    end

    always @* begin
     LED =  state;
    end


endmodule

The testbench module is here

`timescale 1ns/1ns


module FPGA_Testing_tb;

     reg clk;
     wire LED;
     reg reset;

     FPGA_Testing test(
                      reset, 
                      clk, 
                      LED
                      );


    initial     
    begin
        clk = 0;
        reset = 1;
        #10
        reset = 0;
    end

    always
    begin
        #5 clk = !clk;
    end


endmodule

My sdc file is here

##############################################################################
# Set resolution and units for timing file:
set_time_format -unit ns -decimal_places 3

##############################################################################
# Create a clock called "yourClockNameHere" (can be whatever you want)
# set its period in nanoseconds, set the waveform as { rise fall },
# and set which port in the design it is.
# The example below describes a 50MHz clock with 50% duty cycle 
# (rise at 0ns, then fall at 10ns) driving the 'clk' top level port
create_clock -name Cy10_Clock -period 2.286 -waveform { 0.000  1.143 } [get_ports { clk }]

# You can make more than one clock if needed.

##############################################################################
# Now that we have created the custom clocks which will be base clocks,
# derive_pll_clock is used to calculate all remaining clocks for PLLs (if any)
# and clock uncertainties.
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty

My qsf file is:

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.1.0 Build 590 10/25/2017 SJ Lite Edition
# Date created = 11:17:48  November 22, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#       FPGA_Testing_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#       assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone 10 LP"
set_global_assignment -name DEVICE 10CL025YU256I7G
set_global_assignment -name TOP_LEVEL_ENTITY FPGA_Testing
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:17:48  NOVEMBER 22, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "17.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL Synplify
set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name VERILOG_FILE FPGA_Testing.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE FPGA_Testing_tb.v
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH FPGA_Testing_tb.v -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME FPGA_Testing_tb.v -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id FPGA_Testing_tb.v
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME FPGA_Testing.v -section_id FPGA_Testing_tb.v
set_global_assignment -name EDA_TEST_BENCH_FILE FPGA_Testing_tb.v -section_id FPGA_Testing_tb.v
set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT ON -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT ON -section_id eda_simulation
set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
set_global_assignment -name SDC_FILE FPGA_Testing.sdc
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name NUM_PARALLEL_PROCESSORS 4


set_location_assignment PIN_R162 -to clk
set_location_assignment PIN_C204 -to reset

set_location_assignment PIN_R138 -to LED

When I compile the code, I get the following error:

Info (21077): Low junction temperature is -40 degrees C
Info (21077): High junction temperature is 100 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Error (171016): Can't place node "LED" -- illegal location assignment PIN_R138
Error (171016): Can't place node "reset" -- illegal location assignment PIN_C204
Error (171016): Can't place node "clk" -- illegal location assignment PIN_R162
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00
Error (171000): Can't fit design in device
Error: Quartus Prime Fitter was unsuccessful. 4 errors, 1 warning
    Error: Peak virtual memory: 5005 megabytes
    Error: Processing ended: Wed Nov 27 13:06:23 2019
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus Prime Full Compilation was unsuccessful. 6 errors, 1 warning
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  • 1
    \$\begingroup\$ Isn't the error obvious ? your pin assignments are wrong. Study the manual and assign pins correctly in sdc with proper names. \$\endgroup\$ – Mitu Raj Nov 27 '19 at 18:35
  • 1
    \$\begingroup\$ What do you see if you open the Quartus GUI and look at the assignment editor? It may be easier to debug if you set the pins through the GUI. \$\endgroup\$ – Charles Clayton Nov 28 '19 at 5:56
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If your board is in the database, Quasrtus should be able to populate the QSF file automatically. When configuring the project, were you able to pick your board from the list?

Presuming that didn't work for some reason, as suggested on your another question, take a look at the doc for your board.

Look for USER_LED0, for example (Ctrl-F works on this doc). It seems connected to pin L14 of the FPGA (and also indirectly to the R138 resistor, which likely threw you off).

Repeat the same for the other pins (the reset looks to be J15 and the clock E1, but please validate), and you should be good to go! Good luck!

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