This is a follow up question to Reason of multiple GND and VCC on an IC

I found a switching regulator IC (buck) that has multiple PGND pins and one analog ground (AGND). It has only one VCC pin. (Sorry, Could not attach a snapshot/datasheet as I could't find a public domain document for the same). Anyways it is a simple buck , with all usual pins + 3 PGND pins.

I understand the need for separate ground for analog circuitry and power circuitry .My doubts are:

  1. What could be the reason for multiple power ground pins?

  2. If this method of multiple ground pins are for higher current capability ( or any other advantage), why is it not followed by many SMPS IC manufacturers? I see many switching regulator ICs ( with similar rating) having single PGND pin.

  3. Also shouldn't the VCC pins have the same count as GND pins?

  • \$\begingroup\$ Fair use (in the US, where Stackexchange is) means you can use a portion of a copyrighted work for discussion of that work. You should at least link to a datsheet giving an example of the situation you're asking about. \$\endgroup\$
    – The Photon
    Commented Nov 28, 2019 at 6:01
  • \$\begingroup\$ How can we assess if the design has merit? \$\endgroup\$ Commented Nov 28, 2019 at 6:08
  • \$\begingroup\$ Sorry, Iam not sure if I violate the confidentiality ,how much ever trivial the case is, if I post the snapshot. The data sheet is not yet available in public domain. \$\endgroup\$ Commented Nov 28, 2019 at 6:16
  • \$\begingroup\$ If the data sheet is downloadable then it’s not your problem - as long as you have no NDA with the vendor. Linking it and excerpting it are fair use. \$\endgroup\$ Commented Nov 16, 2022 at 15:49

3 Answers 3


Two reasons.

  1. The PGND path is where the low-side sync n-FET connects. During the inductor discharge cycle, PGND is taking the entire return from the inductor, load and output filter cap. With a step-down it also conducts most of the time, and so is chosen to have an even lower Rds(on) than the high-side FET. So low inductance and resistance on PGND help that FET’s performance.

  2. Thermal. The more low-impedance GND pins are connected to a GND plane, the more heat is carried away from the device.

The high-side FET can benefit from low inductance too, but it doesn’t get slammed into ‘on’ as hard or as quickly as the low-side sync FET, so it can get by with fewer pins (or in this case, just one.)

The reason the high-side FET doesn’t get slammed as hard is that its current path is much longer - all the way from the power supply, through the high-side FET, through the inductor, into the load, and back to the power supply.

Thus, the high-side FET’s VCC lead inductance is a relatively small parasitic contributor to that large loop’s parasitics, and is therefore less critical than the low-side FET’s PGND connection.

The high-side switching current is still peaky though, which is why input bypassing is still needed, but still much less than the output filter cap.

Below is a sim showing a COT-type step-down sync buck regulator (simulate it here):

enter image description here

You can see that both FETs see high peak currents, but the lower FET has a much higher average current due to the step-down ratio. So any losses in PGND vs. VCC will be much greater.


You're talking about a buck converter. In a buck converter the output current is usually larger than the input current. A buck converter which is converting 10 V to 5 V will draw half of the load current.

Example: input = 10 V, 1A; output = 5 V, 2A

Note how the input current is half the output current.

So for the output current path, having a low series resistance is more important in two ways:

1) the current is higher so at a given series resistance, the voltage drop (per pin) is higher


2) even if the voltage drop is the same, say 100 mV then at 10 V that is only 1% (of 10 V) but at 5 V that same 100 mV is 2% of the (5 V) voltage.

So any voltage drop is more significant at the output side.

Also, a voltage drop at the input VCC pin isn't even significant, the regulation function of the buck converter will compensate for that voltage drop.

If you think about how currents flow (mind that currents always follow a closed loop) and how large they are then the reason why having multiple PGND pins becomes obvious.


A regulator chip senses output voltage, its difference from an internal reference voltage determines the correction requirement. So, if a power-carrying ground pin has even just a few millivolts of resistive voltage drop between the circuit board and the silicon chip, THAT could cause a regulation error by adding to the voltage reference.

To combat that, a second ground pin could be used, for the voltage reference, so that there is a low-current wire bonding that second ground pin for improved accuracy. Less often, the ground voltage from a second sense wire that attaches to the distant load is the 'common' connection for such a reference voltage (but wouldn't be labeled as 'gnd'). A/D converters, too, may have both a 'digital ground' and 'analog ground'.

Sometimes a pin can be used at the factory for an adjustment, or test, but has no useful function in normal chip operation; the grounding of such an unused (but possibly sensitive) circuit node can be strongly recommended. Labeling such a pin 'gnd' ensures compliance.


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