# Coupling capacitors in a CE amplifier

I know that those C2 and C3 are used to isolate DC from the input and output. Capacitors are always open to DC(w=0) and since the equivalent impedance of a capacitor can be expressed as 1/jwc in frequency domain, to get a low impedance(almost short circuit), I think to use a larger capacitance value like 100F. I know in reality 100F is not a so logical value for common capacitors, however, I use LTspice program and it is easy to use a 100F in a simulation. So I enter 100F for the values of C2 and C3. However, when I do that the results get creepy.

The Vout waveform for 100uF C2 and C3 is a nice sinusoidal wave with gain > 300 ( 620 mVpp nice looking sine wave ) .

But for 100F C2 and C3, the result is,

So, why is this the case? Why using a higher capacitance is not a better thing?

p.s : I hope they were called as "coupling" capacitors.

• Ah , LTSpice interprets 100F as "100 femto-farads"...a very tiny capacitance. If you substitute 100, LTSpice should interpret that as 100 farads. Commented Nov 29, 2019 at 18:34
• I guess it was the problem. This time I can get more meaningful results. But now, the sine wave is not centered at 0. Instead it is between 3.3 to 3.9 volts. Commented Nov 29, 2019 at 19:01
• With nothing to pull-down the output side of C3, the initial DC bias point assumes a DC voltage drop across C3 as zero, so you see Q1's collector voltage on both sides of C3. Try adding a large pull-down resistor to ground on C3's output side...then you should see average output of zero. Note that LTSpice's default is to do a DC bias solution first and then proceed with transient from there. You can change the default transient analysis to start DC supplies at zero. In this case, all capacitors would start off discharged...before V1 rises to +12V. Commented Nov 29, 2019 at 19:30
• Sometimes you want to see the start-up thump - use start DC source @ 0. I suspect you want to see quiescent operation. If you allow start DC source @ 0 then your simulation runs for hundreds of seconds before settling (with 100uf coupling capacitors, or many hours with 100 farad coupling capacitors). ugh. That's when you start DC sources already applied. Commented Nov 29, 2019 at 21:11
• R1,R2 are a bit too big. If Base Zin =hFE*Re and hFE=100 the Zin = 47k loading down Rb_eq=171k H-bias, then with C on Re the AC input impedance is also low so the source must be a buffered signal or a sig gen (50 ohms) Commented Nov 29, 2019 at 21:13