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enter image description here

The circuit is not important, my quesiton is for example, for C3, while using an electrolytic capacitor(I assume for a 100uF, electrolytic is the most common one); which side should be connected to the + terminal of the capacitor? Right or left? Why?

Thanks.

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    \$\begingroup\$ That would depend on where it is connected to, or more specifically, what is the DC bias voltage over the capacitor. Can you give an example situation where would you connect it? And by doing so, you might also already see what is the correct polarity. \$\endgroup\$
    – Justme
    Commented Nov 30, 2019 at 13:56
  • \$\begingroup\$ @Justme for example we were connecting oscilloscope probe to that Vout node in the lab. However, I never get which side of the capacitor will be at higher potential. \$\endgroup\$
    – muyustan
    Commented Nov 30, 2019 at 13:57
  • \$\begingroup\$ Well what is the DC bias on the transistor collector? Is it zero, positive or negative? What is the DC bias on scope input? Is it zero, positive, or negative? \$\endgroup\$
    – Justme
    Commented Nov 30, 2019 at 14:01
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    \$\begingroup\$ Ignore all capacitors for now and assume \$h_{fe}\$ is large so the base current is negligible. What base voltage does this give you? From here you can get the emitter voltage and hence current in Re. The same current flows in Rc so what is the collector voltage? Does this answer your question? \$\endgroup\$ Commented Nov 30, 2019 at 14:01
  • \$\begingroup\$ @Justme I assume these are questions for me... So, the left side will be positive side. \$\endgroup\$
    – muyustan
    Commented Nov 30, 2019 at 14:07

3 Answers 3

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The pictures below can help understanding the problem. Voltages and voltage drops are visualized by vertical bars (in red) with corresponding lengths, and currents - by loops (in green) with corresponding thicknesses.

After the power supply is turned on, the output decoupling capacitor C2 is charged by the current IL flowing along the loop E+ -> Rc -> C2 -> RL -> E-. Similarly, the input decoupling capacitor C1 is charged by the current IG flowing along the loop E+ -> RB -> C1 -> EIN -> E-.

AC_zero_input

C1 and C2 retain their charges (voltages) during the positive half-wave...

AC_positive_input

... and during the negative half-wave:

AC_negative_input

These pictures are combined in the more sophisticated picture below:

AC amplifier visualized

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The amplifier output has positive DC bias. If it is connected to something that has less DC bias, then capacitor positive side would be on amplifier output.

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  • \$\begingroup\$ can any load(resistive,inductive etc., no sources included) be considered as having less DC bias ? \$\endgroup\$
    – muyustan
    Commented Nov 30, 2019 at 15:06
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    \$\begingroup\$ Only if it is connected to voltage less than output bias and it has a DC path through it. For example a speaker or resistor between output and 0V would be biased to 0V. \$\endgroup\$
    – Justme
    Commented Nov 30, 2019 at 18:06
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    \$\begingroup\$ I prefer Justme's answer here. It covers the situations better. The load may be tied high or tied low. So, "it depends." \$\endgroup\$
    – jonk
    Commented Dec 1, 2019 at 4:59
  • \$\begingroup\$ C2 acts as a kind of "rechargeable battery" with equal but opposite (to DC bias) voltage. This "anti-source" is connected in series and contrary to the bias collector-emitter "source"; so it neutralizes its voltage and the resulting voltage across the load is zero. If the load is connected to V+ instead to ground, the capacitor is connected in parallel to the VRc bias voltage and would be charged with an opposite polarity; so it should be reversed (with its "-" to the collector). The load must be galvanic (low resistive) since the capacitor is charged through it and this is a "dead" time. \$\endgroup\$ Commented Dec 2, 2019 at 6:35
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Yes, the positive lead of the capacitor is at the collector of Q1. Whether the capacitor lead on the right side of the cap [as shown in the circuit] is going to any other component or just 'up in the air' its opposite lead is at the collector of the NPN transistor and that is a positive potential. [I know that I should know my electronics theory better but I've been working in electronics for over 50 years and I know that that this answer is correct]

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    \$\begingroup\$ It is not always so. If the load is for example a second BJT amplifier stage with higher input DC bias then cap would be the other way. Your answer also assumes that the load is returned to ground or some other more negative voltage. \$\endgroup\$
    – Justme
    Commented Dec 2, 2019 at 6:44

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