I have this XOR circuit: enter image description here

I tried to write it using only NAND gates and this was the furthest I got: enter image description here

According to my book, it should look like this: enter image description here

I did this: $$(x.y')+(x' . y) = ( (x. y')+(x' . y))'' = ((x. y')'.(x' . y)')'$$

Which is the second circuit. I know NOT gates can be done with NAND gates but you'd have to use 2 in this case and the book only uses one. How do I do that?


That's just a trick to save one NAND gate. The output of the top leftmost NAND gate in the second picture is \$Z_1=(x.y')'\$ and of the down leftmost is \$Z_2=(x'.y)'\$. Now \$Z_1\$ and \$Z_2\$ can be re-written as \$(x.x'+x.y')'\$ and \$(y.y'+x'.y)'\$ respectively. Simplifying the two yields \$Z_1=(x.(x.y)')'\$ and \$Z_2=(y.(x.y)')'\$. The latter two expressions for \$Z_1\$ and \$Z_2\$ are what can be inferred from the third picture.

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