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What's the difference between a += 1 and a = a+1 in SV/V?

always_comb begin a = '0; a += 1; end

always_comb begin a= '0; a = a+1; end

Is 2nd case combinational loop?

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  • \$\begingroup\$ It's the same thing. Just make sure you don't mistake += with =+ because those expressions are different. \$\endgroup\$ – KingDuken Dec 3 at 6:19
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a+=1 is just a short-hand for a=a+1. They both are equivalent.

There is no combinational loop in both cases.

a will be simply driven 1 in both cases. Synthesiser usually flags this as warning or info.

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These are equivalent assignment statements in SystemVerilog—there is absolutely no difference. And the two always_comb blocks do absolutely nothing as they have no sensitivity to any variables. In fact, some tools may generate warnings or errors stating that the blocks do not represent combinational logic.

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    \$\begingroup\$ The always_comb will run once per IEEE1800-2017 § 9.2.2.2.2 always_comb compared to always @* "always_comb automatically executes once at time zero, whereas always @* waits until a change occurs on a signal in the inferred sensitivity list." \$\endgroup\$ – Greg Dec 3 at 16:30
  • \$\begingroup\$ Yes, that's true for simulation. Not sure how synthesis tools treat time 0 behavior \$\endgroup\$ – dave_59 Dec 3 at 16:32

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