What's the difference between
a += 1 and
a = a+1 in Verilog?
always_comb begin a = '0; a += 1; end always_comb begin a= '0; a = a+1; end
Is the 2nd case a combinational loop?
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These are equivalent assignment statements in SystemVerilog—there is absolutely no difference. And the two
always_comb blocks do absolutely nothing as they have no sensitivity to any variables. In fact, some tools may generate warnings or errors stating that the blocks do not represent combinational logic.