# How a Cmos not gate works

This is a very newbie question, but i don't understand it well, and i'm studying a lot! =(

I have a Cmos not gate, and I don't understand well how it works.

Dividing in cases:

case X = 0V: the nMos if off and from pMos to Z arrives High Voltage. Ok.

case X = 5V: here is the problem. pMos is off, and nMos is on. If nMos is on, it should arrive to Z high voltage because it is on!

But this is my mistake, i know. Can someone please, patiently, explain me this?

Thanks a lot.

• Please post the diagram showing what you mean by "X" and "Z". I can't follow you at "pMos is off, and nMos is on. If pMos is on," - is pMos off or on? – pjc50 Nov 1 '12 at 16:29
• I think what you are calling a "not gate" may be a inverter? If so, you should be able to get lots of basic information on CMOS inverters out there. In its simplest form, a CMOS inverter is just two transistors. – Olin Lathrop Nov 1 '12 at 16:38
• Yes, it is an inverter. Sorry for mispelling, i'm not english. – user15781 Nov 1 '12 at 16:40
• When input x is 5V PMOS is in off state, so that PMOS has high impedance no current conduct in PMOS. if PMOS is in off state output is 0V because VDD is given at PMOS. – smita adhikari Oct 4 '20 at 14:24
• @smitaadhikari As a simple illustration of the error, consider if the gate you propose were to drive a pullup resistor. Given the lack of anything to sink current, the output would always be high - either because the PMOS is on, or even when the PMOS is off, because the pull-up resistor is pulling it high anyway. Now substitute an actual CMOS structure and you'll see that it is the presence and activation of the NMOS which allows the output to drive low against the pulling resistor. – Chris Stratton Oct 4 '20 at 22:53