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If the capacitive DAC on the ADC uses Vref, would it not output a signal from 0 to Vref to the comparator? How would the comparator work if the input signal is greater than Vref since it would always output all 1's.

The AD7914 allows the input of the ADC to be 0 to Vref or 0 to 2xVref by changing a bit in a register.

Does it use an internal resistor divider to reduce the input by half?

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For 2's complement or unsigned SAR conversions always use the "remainder voltage" /2 to decimate then next bit. So I believe using Vref/2 as the comparator level for SAR conversion is normal and the input full-scale is 0 to Vref. i.e.

  • MSBit conversion 0 means < Vref/2 and 1 means >= Vref/2

In this chip Vref = 2.5V and the logic supports 3V and 5V supplies however if the the user sets 1 bit in a register to indicate 2xVref is going to be used i.e. 0~5V analog in, then the logic supply MUST BE 5V. This feature prevents the comparator from having to do level shifting down and prevents over-voltage to the logic side where the analog comparator drives the logic in successive approximation register ( SAR )steps. So the analog input range comparator input must not exceed the logic supply.

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