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Why in designing of CMOS logic we only consider the capacitive load of fanout? There is some wire resistance. So, why don't we consider resistive load?

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    \$\begingroup\$ In some cases we do consider resistance, often adding external resistors to improve signal integrity. \$\endgroup\$ – Cristobol Polychronopolis Dec 4 '19 at 19:31
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When the wiring resistance becomes significant, then we do include it. As long as the wiring resistance is much, much less than the \$R_{DS}\$ of the MOSFET then it can be ignored.

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Wiring resistance is usually less than 1Ω and most wiring resistance being in the mΩ range. With many digital logic families maxing out at 50mA, if you were to calculate the equivalent resistance of most push pull GPIO's, the source resistance would be somewhere in the range of 100Ω to 50Ω at DC. Because of 50Ω is much bigger than mΩ's the wiring resistance can be neglected in allmost all cases.

However, if you have long wires or small wires that make the wiring resistance more than ~1Ω then you should consider wiring resistance in your calculation.

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We do. Internal to the CMOS chips, the resistance of the deep-sub-micron metal layer wiring contributes significantly to the RC delays even a small distance across an SOC (less than 1mm) in or between logic blocks. That analysis is a large part of timing closure to meet clock rate specs.

In PCB design, another consideration is inductance: mutual inductance can be a cause of crosstalk between long traces, reducing signal integrity. Trace inductance can also contribute to ringing of steep transients, causing signal under/overshoot.

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Why C and not R, what about Zo = sqrt (L/C)?

  • Attenuation occurs when the source impedance is not zero or the load is not infinity. Although 5V logic is around 50 Ohms is considered low relative to the expected gigaohm gate input resistance so we can neglect trace resistance as well as load resistance.

5V (1Gohm)/(1 GOhm + 50 ohm) = 5V as a voltage divider on R there is no attenuation , so we neglect load R.

  • Impedance of CMOS transmission signals do matter when the 2~3ns rise time reduces to make reflection echos visible in the echos from mismatched Z load reflections. These delays show as 35% typ overshoot & decayed ringing unless terminated with matched impedance.

However increased risetime and for longer traces , ringing can degrade signal quality.

  • Typical trace width, W with a height, H over ground planes and trace length , L has an impedance based on ratios of these parameters.

When typical PCB FR4 trace geometry has a ratio H/W=2, Zo = 83 Ohms, L < 5 nH/cm , C ~ 0.7 pF/cm with a propagation speed, v = < 18 cm/ns (Ref Saturn PCB.exe)

  • Rise time, Tr is defined as the 0 to 64% Vmax by a standard T=RC load capacitance (e.g.15pF) and the logic family standard source resistance. For 5.5V logic this is 50 Ohms +/-50% and for 3.6V logic this is 25 Ohms +/-50% typically. Lowering the gate + supply voltage increases RdsOn so 3.6V logic was designed to use a lower Vgs(th) and lower RdsOn to improve rise times but then cannot be used at 5V as it would go into shoot-thru or cross-conduction with both hi & lo side drivers active.

  • Tr = RC is the rated at 15pF but your design may be more or less depending on trace width over ground planes, trace length , fan out of gate loads and logic family.

  • Ringing occurs when the prop delay approaches the rise time the mismatched load reflection causes an observable change with oscillation.

When the signals go on cables, we are either limiting the data rate and slew rate (e.g. RS-232) or we terminate the cable with a load resistance matched to the cable ( e.g. 120 Ohms for ribbon or 50 typ. for coax.)

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CMOS logic input draws no DC current, so there is not much resistance or resistive load to consider when a CMOS output drives CMOS inputs. The speed how fast a signal can transition between states depends mainly on output current drive strength and capacitances it needs to drive. PCB wiring has very little resistance in comparison, though wiring does add capacitance easily.

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Resistance is included, in the sense that the output voltage level of a CMOS device is specified at a given current. From these two numbers, the output resistance of the device can be estimated, and from that you can assess the effect of an ohm or two of wiring resistance. Here's an example from a 74C04 data sheet. enter image description here

Note the Voh is spec'd to be at least 2.4 V at a current of -360 uA. You'll find a similar set of specs on almost any digital device.

The capacitance has to do with how fast a device can change the voltage on a node. It's a dynamic, switching, or AC specification. This spec impacts how fast a circuit can switch (though it's not the only thing), and also impacts the dynamic power dissipation of the device.

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