65V Square wave Switching Circuit

Question

I am trying to generate a 65V square wave very similar to the post found here: Mosfet PWM signal not square

My load is in a slightly different configuration (i've tried them both ways), but the problem I am having is very similar to the original poster in that the link above.

Basically I'm switching a FET that is in connected to a 65VDC supply through a 10K resistor and placing my load across the FET. Here is my circuit:

Here are my scope shots. The blue is voltage across the load and the yellow is the gate signal.
I'm inquiring how I can make that rising edge across the load fast and sharp. The rounded edge makes me unable to achieve 65V when I increase the switching frequency since the capacitance in the load and my resistor causes the voltage across the load to rise too slowly. The screenshots show about a 60Hz frequency, but I'd like to get up to about 10 kHz.

My load is a PLDC diffusing film and there is about 1 uF worth of parasitic capacitance built into the material which I cannot remove. I am also aware that I can reduce the 10K ohm resistor at the drain of the FET, but since my peak voltage is 65V, reducing the resistor begins to put quite a bit of power on that resistor which I'd like to avoid.

The only other way I can think to make this happen is by putting another FET in parallel with the drain resistor and syncing and inverting the gate signal of this other FET such that it will turn on when the other one turns off and vice versa.

But is there a better way than this?

I tried putting the load in place of the 10K ohm resistor with the voltage developing across the load being less. In regards to the FET not being turned on completely, I am using a frequency generator and have increased the turn on voltage to 10V with no different results so I don't think that is the issue. See my scope shots below. Yellow is the gate drive, Blue is the voltage across the FET, Purple is the high (65V), and red is the voltage across the load.

Answer 1

I can think of 2 filter approaches:

1) an impedance controlled RLC filter for maximum power transfer thus 50% efficiency, using C as load

2) A RLC filter based on user's rise time requirement at given f, Vpp
- thus dV/dt =Ic/C and dI/dt=V/L with low Q <2 and lower loss - but higher peak power demand for same energy stored in C load.

Using 1)

• with a period of 100 us cycle and 10us rise time at 50% efficiency

• compute the average power dumped in R.

  • E=0.5CV² = 0.5 * 1uF * 65V² = 2.1 mJ = 2.1 W-us means 21 Watts in 10us
  • thus here is a quick & dirty design

Answer 2

I am also aware that I can reduce the 10K ohm resistor at the drain of the FET, but since my peak voltage is 65V, reducing the resistor begins to put quite a bit of power on that resistor which I'd like to avoid.

You can avoid some of the power loss, but not all of it. Whenever a capacitor is charged or discharged through a resistor there will always be a power loss, as only 50% of the energy goes into changing the charge on the capacitor. The other 50% is dissipated in the resistance.

I simulated your circuit in LTspice with a 65V supply, IRF530 and 10kΩ pullup resistor, driven with a 58.65Hz square wave. Unfortunately with 1uF capacitance the curve didn't match your display, so I fitted it by eye - which required 330nF. With these values the 10k resistor dissipated 254mW and the MOSFET drew a peak current of 85A when discharging the capacitor (way over its rating!).

Then I increased the frequency to 10kHz and lowered the resistor value to 60Ω. This produced a similar waveform but the resistor dissipated 42W, 35W of which was due to it being pulled down to ground while the FET was turned on.

To remove that unnecessary loss I created a half bridge circuit with 2 MOSFETs, putting the 60Ω resistor in series with the capacitor and switching it alternately between Ground and +65V. Voltage on the capacitor then swung from +5V to +60V, and the resistor dissipated 12W. The rms power supply current was 320mA. Since that voltage swing wasn't quite enough I then reduced the resistor value to 30Ω, which got the voltage swing within 0.5V of the supply rails. This increased resistor power dissipation to 14W and rms current draw to 490mA.

Once you get to the point where the capacitor is fully charging and discharging, speeding it up further won't significantly increase power consumption (unless you increase the frequency). The only bad effect is increased peak current. With resistance reduced to 15Ω the waveform starts to look reasonably 'square' and power dissipated in the resistor is still only 14W, but rms power supply current increases to 700mA. The IRF530's now draw a peak current of ~4.5A each, which is within their safe operating area.

If 14W is still too much loss then the only other option is to use some inductance to form a tuned circuit with the capacitance. Any energy put into a tuned circuit will circulate around it, increasing the voltage without wasting power. However this will make the result critically dependent on the capacitance, inductance and driving frequency, as well as any other parasitic elements (film resistance, wiring inductance, dielectric effects etc.).

Answer 3

Look up “complementary gate driver integrated circuits”, use two high voltage FETS in a totem pole configuration. The data sheets will have example circuits.