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I am using this QSPI Flash Memory IC

I'm operating the QSPI clock at 48MHz. I am probing the Clock and Data signals in my scope.

On Table 54 which is on Page 128, we have Rise time and fall time specifications. But the specification is given in terms of slew rate instead of seconds. How to convert it into seconds format.

I tried doing the below approach :

Considering figure 12.4.1 in page 129, rise time and fall time are given with respect to Vil max and Vih min which is 0.99V and 2.31V respectively.

So, 2.31V-0.99V = 1.32V.

But rise time is given as 0.1V/ns.

So, if 0.1V is for 1 ns, then 1.32V should have a rise time of 13.2ns?

I think this is wrong approach. Can someone help me with this on how to find the rise time in terms of seconds instead of slew rate?

Waveforms (Please check the Y-cursor is kept as per the Vil max and Vih min as per the table)

enter image description here

enter image description here

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  • \$\begingroup\$ Your approach is correct. \$\endgroup\$
    – Wheatley
    Dec 5, 2019 at 11:51
  • \$\begingroup\$ Ok thank you. So, I should have a minimum Rise time of 13.2ns and maximum is not mentioned in the datasheet. This doubt arised because I have a rise time 1.12ns and fall time as 940ps. Is this correct? I will attach the waveform images in my question now \$\endgroup\$
    – user220456
    Dec 5, 2019 at 12:05
  • \$\begingroup\$ You didn't say if the rise time of 0.1V/ns is a max or min spec. Since this is for a clock input, they usually like fast edges. A slower edge rate than spec'd could cause the device to double clock as the clock signal transitions through the switching region. \$\endgroup\$
    – SteveSh
    Dec 5, 2019 at 13:02
  • \$\begingroup\$ As per the datasheet, the rise time and fall time is mentioned under the Min. column \$\endgroup\$
    – user220456
    Dec 5, 2019 at 14:11

1 Answer 1

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The clock input rise and fall times are the minimum required for the device to properly respond, so whatever is driving this pin must provide at least that transition rate. A faster rate would be quite acceptable.

The note states 84. Full VCC range and CL = 30 pF. This means that the full transition must occur (for 0 to 3.3V or vice versa) in a time equal to or less than 33nsec but this is for proper internal operation and does not consider data rates.

At 48MHz, each bit is 20.83 nsec, but this is not a contradiction - clearly the clock pin needs to be driven faster than the minimum required to achieve this data rate which is what your scope picture shows (almost sinusoidal with full rise and fall each taking about 10 nsec - i.e. your clock transition rate is faster than the minimum required).

Your clock is, therefore, within the limits imposed by the manufacturer.

it is not at all unusual to require minimum transition rates on inputs to CMOS devices (slow transitions can damage the device). This application note goes into some detail.

You can get a lot more insight into the device (particularly the data drive) from the IBIS model. The SCK input has the model name [Model] F_SCK

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    \$\begingroup\$ One important thing to add: The rise time seem in the image is likely caused by the bandwidth limitation of the oscilloscope and probe rather than the device being measured. \$\endgroup\$
    – Timmy Brolin
    Jan 7, 2020 at 14:41

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