This is a question related to swapping a 74LS170 4 x 4 register file chip for a 74LS173 single 4-bit register. In the other question I wonder if there are even simpler ways to Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous. But here I need to deal with the issue that the 74LS170 is an open collector chip (and for now I am unable to get the '670, which is a three state).

I read a number of things about open collector, and especially the other pretty decent entry here Understanding Proper Implementation Of Open-Collector. However, I think I need to get spelled out a clear "yes" or "no" answer to my following doubt:

If you want to drive further TTL inputs from open-collector output, you need to consider your signals effectively inverted.

In other words, you can tie the open collector output pin high, and then when it is active it will be pulled low through the enabled transistor. There is no way to source current from an open-collector output.

Hence, if I want to use the 74LS170 as an actual register file, I need to also use an inverter for the 4 bits. It just so happens that if I actually want to turn the 74LS170 into a synchronous register whose load is driven by the positive clock-edge, I need the inverter anyway, along with an OR gate. So there simply is no other way.


simulate this circuit – Schematic created using CircuitLab

Or is there?

As a bonus question: the '670 was developed much later, supposedly, and it has 3-state output, so it no longer effectively inverts the output. But why in the world would they not have driven that by a positive clock edge, instead of using the pin for the 3-state logic? I mean, nobody could have just dropped in the '670 for the '170 because the sense of the output bits are inverted. Why even bother with the 3-state then? I feel that the answer to this question might help me appreciate the annoying situation with the open-collector need for inverters.

Or, another one of those pleading questions: was the open collector output so much easier to do that they would determine that it's better this way than to let the user add their own (power) transistor to adapt to voltage and current levels?

And finally an idea: perhaps this explains the odd customs with these active-low signals on most "load" or "write enable" pins of most flip flops and SRAM and EEPROMs? And from there, perhaps, by using open-collector OR gates instead of normal TTL outputs, I effectively get NORs and other inversions which might simplify my clock edge detection IC overhead?

Yet another possible explanation: if the register file's output is expected to be output onto a bus, were the original designers expecting that it be connected as an effective NAND gate with the other devices on that bus? Still can't quite see the rationale for this.

Final whining question: so why in the world would I even want to use the 74LS170 (even decades ago) when with all the work I need to go through I can just as well adapt the 74LS189, fitting it with a clock edge detector and the inverter, using the same number of chips I get 16 instead of just 4 registers? (OK, because I can not read from one address and write to another in the same cycle, fine.)

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    \$\begingroup\$ In this particular case, the outputs are not inverted; there is a prior inversion before the open collector output so that in transparent mode, Qn = Dn (i.e. if the input is high, the output will also be high provided it is pulled up). If you look at the logic diagram, internally the the '170, we actually store NOT D. docs.isy.liu.se/pub/VanHeden/DataSheets/sn74ls170.pdf \$\endgroup\$ Dec 7, 2019 at 15:01

2 Answers 2


The 74LS170 is not inverted from input to output even with the open collector outputs when looked at logically (i.e. input pin to output pin); the datasheet truth table shows it, but a better source is the logic diagram.

74LS170 Logic Diagram

Looking at the inputs (at the top), the inputs are inverted prior to storage (in the red ellipse) and therefore what is actually stored in the internal latches is \$ \overline D_n\$

When reading the data back out, the effective open collector inversion (in the blue ellipse) converts the stored data back to the original input.

Open collector predates tri-state outputs by some time (possibly decades) and was used primarily for bus applications (so that one of many outputs could drive a single signal line); tri-state achieves the same thing but by disconnecting the output from the signal line, but came much later and when it first showed up there was a significant price premium and it had it's own issues when used (the timing between driving nodes needs to be controlled so that we don't get bus contention; an issue that is irrelevant in open collector architectures).

That does not mean we don't have to take timing into account - we do but in open collector there won't be any damage to parts if two (or more) outputs happen to be driving the same line at the same time, so from that perspective it is much easier.

The concept of Wire-OR (or really wire-AND) was specifically designed so that we could have an effective output gate on a bus as effectively a data selector [we needed to know which output we had selected. of course] (apart from the numerous other applications it is used in).

As noted in comments on your other question(s), when the '170 came out it had designers drooling (dual port, read from one register while writing to another enabling primitive pipelining) - it really was a 'wow' part at the time.

As you note, the '670 came out quite a bit later (when tri-state was more the norm in bus architectures and had become the de-facto standard and the price had dropped).

Tri-state has advantages of course; rise and fall times are close to equal because they are actively driven for both high and low (in open collector the effective RC time constant had to be evaluated for how fast the signal line would rise back to a high).

So it is a mixture of target application and history as to which type of output is suitable.

The 74LS189 was introduced (if memory serves) around 1980, some years after the '170 (almost 10 I believe).

Open collector is also often used in window comparator circuits, incidentally.

  • \$\begingroup\$ This is very interesting, thanks! Strangely though, the datasheet of the 74LS670 shows the exact same arrangement with inverted D inputs and the final NOR gates on the output side. So what exactly is it about the data sheet that would suggest that to compensate the open-collector issue, it will keep the final transistor shut disabled for logic 1 and enabled for logic 0? Is it simply always assumed in any open collector chip? I don't think it is for open collector buffers, especially not the ones you use to drive high voltage things like Nixie tubes? \$\endgroup\$ Dec 7, 2019 at 18:18
  • \$\begingroup\$ The '670 datasheet would probably have been given the same logic diagram to show identical operation (apart from Tri-state outputs). \$\endgroup\$ Dec 7, 2019 at 18:21

I think I operated with a misunderstanding. Just reading the Wikipedia page https://en.wikipedia.org/wiki/Open_collector it is now beginning to be clear to me that the usual mapping of logic values is taking this inversion into account already. It says:

"On schematic component symbols, the open output is indicated with these symbols:[1]

  • ⎐ for a pin that outputs low-Z L or hi-Z H (or ⎒ with an internal pull-up resistor)
  • ⎏ for a pin that outputs hi-Z L or low-Z H (or ⎑ with an internal pull-down resistor)

[...] Another advantage is that more than one open-collector output can be connected to a single line. If all outputs attached to the line are in the high-impedance state, the pull-up resistor will hold the wire in a high voltage (logic 1) state. If one or more device outputs are in the logic 0 (ground) state, they will sink current and pull the line voltage toward ground."

So we have to look for this diamond symbol with the underline. Which doesn't appear in the data sheet by Motorola, but I guess that is the convention.

So this means, the short answer to my question should be "no"! The open-collector does not imply logical inversion when used with a pull-up resistor. It would, however, if we were trying to drive signals with the current through this transistor. Hence the choice of open collector buffers or inverters if we wanted to drive LEDs, bells, whistles, or Nixie tubes.

  • \$\begingroup\$ The Motorola datasheet is from a time when it was Motorola semiconductor sector - MOT-SPS. They have not been that for many years; since it was spun out into On Semiconductor in fact (who inherited the 'basic' logic) which occurred in 1999 (20 years ago). The symbol convention for tristate and open collector outputs did not exist at the time the datasheet was written and was probably never updated. \$\endgroup\$ Dec 8, 2019 at 15:55

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