This is a question related to swapping a 74LS170 4 x 4 register file chip for a 74LS173 single 4-bit register. In the other question I wonder if there are even simpler ways to Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous. But here I need to deal with the issue that the 74LS170 is an open collector chip (and for now I am unable to get the '670, which is a three state).
I read a number of things about open collector, and especially the other pretty decent entry here Understanding Proper Implementation Of Open-Collector. However, I think I need to get spelled out a clear "yes" or "no" answer to my following doubt:
If you want to drive further TTL inputs from open-collector output, you need to consider your signals effectively inverted.
In other words, you can tie the open collector output pin high, and then when it is active it will be pulled low through the enabled transistor. There is no way to source current from an open-collector output.
Hence, if I want to use the 74LS170 as an actual register file, I need to also use an inverter for the 4 bits. It just so happens that if I actually want to turn the 74LS170 into a synchronous register whose load is driven by the positive clock-edge, I need the inverter anyway, along with an OR gate. So there simply is no other way.
Or is there?
As a bonus question: the '670 was developed much later, supposedly, and it has 3-state output, so it no longer effectively inverts the output. But why in the world would they not have driven that by a positive clock edge, instead of using the pin for the 3-state logic? I mean, nobody could have just dropped in the '670 for the '170 because the sense of the output bits are inverted. Why even bother with the 3-state then? I feel that the answer to this question might help me appreciate the annoying situation with the open-collector need for inverters.
Or, another one of those pleading questions: was the open collector output so much easier to do that they would determine that it's better this way than to let the user add their own (power) transistor to adapt to voltage and current levels?
And finally an idea: perhaps this explains the odd customs with these active-low signals on most "load" or "write enable" pins of most flip flops and SRAM and EEPROMs? And from there, perhaps, by using open-collector OR gates instead of normal TTL outputs, I effectively get NORs and other inversions which might simplify my clock edge detection IC overhead?
Yet another possible explanation: if the register file's output is expected to be output onto a bus, were the original designers expecting that it be connected as an effective NAND gate with the other devices on that bus? Still can't quite see the rationale for this.
Final whining question: so why in the world would I even want to use the 74LS170 (even decades ago) when with all the work I need to go through I can just as well adapt the 74LS189, fitting it with a clock edge detector and the inverter, using the same number of chips I get 16 instead of just 4 registers? (OK, because I can not read from one address and write to another in the same cycle, fine.)