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During system initilization software enumerates the different buses, devices and functions with the help of two I/O Ports (CONFIG_ADDRESS 0xCF8, CONFIG_DATA 0xCFC) and two configuration cycle types.

Type 1 PCI Configuration Cycle

Type 1 PCI Configuration Cycle

Type 0 PCI Configuration Cycle

Type 0 PCI Configuration Cycle

PCI-PCI Bridge Numbering example

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Now, when system software writes the corresponding value for bus number 1, device 0, function 0 and register 0 into I/O Port CONFIG_ADDRESS, the PCI bridge with secondary bus number 1 configured receives a type 1 configuration cycle with this information and creates a type 0 configuration cylce on bus 1. Because bits 31:11 are used to select the appropriate device with the help of the ID selection technique, every pci device on the bus has as IDSEL pin which is uniquely hardwired to one of 21 address pins, which correspond to bits 31:11 in type 0 configuration cycle. So bit 11 would select device 0, bit 12 would select device 1 and so on.
Now, every text, explanation, ... I have read, states that a bus can handle up to 32 devices which seems pretty obvious because in type 1 configuration cycles 5 bits (15:11) are used to encode the device number but in type 0 configuration cycles these 5 bits are mapped to one of the 21 bits of a type 1 configuration cycle. However, this limits the maximum number of possible devices to 21. So what is the real device limit?

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    \$\begingroup\$ I avoided your long discussion (I didn't actually read it -- admitted.) There is an electrical limit to PCI due to capacitance loads. The chipset supports \$100\:\text{pF}\$ total (or did, in the day.) Since the connectors themselves represented \$10\:\text{pF}\$ each and the boards tied into PCI were themselves allowed another \$10\:\text{pF}\$ each, when you added in the \$10\:\text{pF}\$ for a "bridge IC" and the \$10\:\text{pF}\$ for the the driving IC, this meant a maximum of 4 boards or slots per PCI. The load allowances were changed for \$66\:\text{MHZ}\$ PCI vs \$33\:\text{MHz}\$ PCI. \$\endgroup\$
    – jonk
    Commented Dec 8, 2019 at 7:53

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When using a physical PCI bus, this mapping scheme indeed limits the number of devices to 21. This is not a problem in practice because that many devices would be too large a load for the bus anyway (see jonk's comment).

This limit does not necessarily apply when you do not have a physical PCI bus. For example, PCI Express connections are point-to-point, so any PCIe bridge/switch that supports more than one downstream port actually has a bridge that connects the upstream port to its internal bus, and, for each downstream port, one bridge to connect the internal bus to the downstream bus. The internal bus is completely virtual (no physical IDSEL pins required) and could use up to 32 devices.

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